SEMICONDUCTOR INTERCONNECT AIR GAP FORMATION PROCESS

• US 20090298256A1
• Filed: 06/03/2008
• Published: 12/03/2009
• Est. Priority Date: 06/03/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei, Tsai, Hao-Yi, Jeng, Shin-Puu
• Granted Patent: US 7,754,601 B2
• Time in Patent Office: Days
• US Class Current: 438/421
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric

Abstract

A semiconductor package including an interconnect air gap and method for making the same. The semiconductor package includes a dielectric layer, a metallic interconnect, an air gap disposed between the dielectric layer and interconnect, and a spacer interspersed between the metallic interconnect and air gap. The metallic interconnect is laterally supported by and isolated from the air gap by the spacer. A method for making the same is also provided.

Claims

1. A method for forming a semiconductor structure comprising:

providing a dielectric layer overlying a substrate;

forming an interconnect recess in the dielectric layer wherein an exposed dielectric sidewall is formed;

treating at least a portion of the exposed dielectric sidewall to form a treated sidewall portion;

forming a non-metallic spacer material on the exposed dielectric sidewall in the recess;

forming a conductive material in the recess adjacent to the spacer material; and

removing the treated portion of the dielectric sidewall to form an air gap between the spacer material and the dielectric layer.

2. The method of claim 1, wherein the treated portion of the dielectric sidewall is dissolved with hydrofluoric acid.

3. The method of claim 2, wherein the hydrofluoric acid is contained in a solution into which the semiconductor structure is dipped.

4. The method of claim 1, further comprising planarizing an upper portion of the semiconductor structure after forming the conductive material to expose the treated portion of die sidewall for removing the treated portion to form the air gap.

5. The method of claim 4, wherein material subtractive chemical mechanical planarization is used to planarize the upper portion of the semiconductor structure.

6. The method of claim 1, wherein the treating step includes using an ashing gas.

7. The method of claim 1, further comprising depositing a photoresist layer above the dielectric layer and patterning the photoresist layer prior to forming a recess in the dielectric layer.

8. The method of claim 1, wherein forming the interconnect recess in the dielectric layer includes using an etching gas.

9. The method of claim 1, wherein the conductive material is copper.

17. The method of claim 1, wherein the recess forming step does not penetrate an etch stop layer or capping layer disposed between the dielectric layer and the substrate.

18. The method of claim 1, wherein the spacer is made of a material selected from the group consisting of SiN, SIC. and SiON.

19. The method of claim 1. wherein the dielectric layer is made of a low-k material.

20. The method of claim 1, wherein the semiconductor structure forms a single damascene or dual damascene interconnect layer.

10. A method for forming a multi-layered semiconductor structure comprising:

forming an etch stop layer on a silicon substrate;

forming a dielectric layer on the etch stop layer;

forming an anti-reflective coating on the dielectric layer;

forming a patterned photoresist layer on the anti-reflective coating;

using an etching gas to form an interconnect recess in the dielectric layer for creating an electrical interconnect, the recess defining an exposed sidewall in the dielectric layer and further exposing the etch stop layer, wherein the recess does not penetrate the etch stop layer;

using an ashing gas to oxidize at least a portion of the exposed dielectric sidewall;

depositing a non-metallic sidewall protective layer on the anti-reflective coating, oxidized portion of dielectric sidewall to encapsulate the oxidized portion, and the etch stop layer;

using an anisotropic etching gas process to remove the sidewall protective layer from the etch stop layer and anti-reflective coating, wherein at least a portion of the sidewall protective layer remains to define a non-metallic spacer;

depositing an electrically conductive material in the recess adjacent to the spacer;

removing the anti-reflective coating to expose at least an upper portion of the oxidized portion of the dielectric sidewall;

removing the oxidized portion of the dielectric sidewall to form an air gap between the spacer and the dielectric layer,

wherein the electrically conductive material is supported by and isolated from the air gap by the non-metallic spacer.

11. The method of claim 10, wherein the oxidized portion is removed by dissolving the oxidized portion with a hydrofluoric acid based solution.

12. The method of claim 10, wherein the anti-reflective coating removing step includes using chemical mechanical planarization to expose the upper portion of the oxidized Portion of the dielectric sidewall.

13. A method for forming a multi-layered semiconductor structure with air gaps comprising:

providing a multi-layered semiconductor package including a silicon substrate, an etch stop layer thereon, a dielectric layer thereon, and a protective coating thereon being resistant to at least ashing to protect the dielectric layer;

forming a recess through the protective coating and into the dielectric layer for receiving a metallic conductor material to form an electrical interconnect, wherein an exposed sidewall is defined in the dielectric layer and the recess does not penetrate the etch stop layer;

oxidizing at least a portion of the exposed dielectric sidewall to form an oxidized sidewall portion;

depositing a non-metallic spacer material on the exposed dielectric sidewall in the recess;

depositing a refractory metal barrier liner over the non-metallic spacer material;

depositing a metallic conductor material in the recess over the refractory metal barrier liner; and

dissolving the oxidized portion of the dielectric sidewall to form an air gap between the spacer material and the dielectric layer,

wherein the refractory metal barrier liner and metallic conductor material are supported by and isolated from the air gap by the non-metallic spacer material.

14. The method of claim 13, wherein the spacer material is selected from the group consisting of SiN, SiC, and SiON.

15. The method of claim 13, further comprising planarizing an upper portion of the semiconductor structure after depositing the conductive material to remove at least some of the conductive material and the protective coating to expose the oxidized portion of sidewall.

16. The method of claim 13, wherein the oxidizing step includes exposing the exposed sidewall to an oxygen plasma ashing gas.