MAC controlled sleep mode/wake-up mode with staged wake-up for power management devices

• US 20090298555A1
• Filed: 08/07/2009
• Published: 12/03/2009
• Est. Priority Date: 03/26/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Edwards, Bruce E., Matson, Mark D.
• Granted Patent: US 8,275,423 B2
• Time in Patent Office: Days
• US Class Current: 455/574
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04W 52/0235 where the received signal is a power saving command
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor'"'"'s control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.

Claims

1. An apparatus comprising:

a processor for a wireless communication device that includes an instruction pipeline; and

a power control logic to detect a sleep instruction and to place the processor in a low-power state after completing any preceding instruction or instructions still in the instruction pipeline, and in which the power control logic is operable in response to a wake-up signal to reactivate the instruction pipeline to process a subsequent instruction following the sleep instruction to perform processing tasks associated with the wake-up signal.

2. The apparatus of claim 1, wherein the instruction pipeline comprises a programmable state machine.

3. The apparatus of claim 1, wherein the wake-up signal is generated from a logical OR'"'"'ing of multiple wake-up conditions.

4. The apparatus of claim 1, wherein the wake-up signal is generated from a logical OR'"'"'ing of multiple wake-up conditions and a time-out interval.

5. The apparatus of claim 4, wherein the wake-up conditions and the time-out interval are stored in a register.

6. The apparatus of claim 1, wherein the power control logic includes instruction decode logic to detect the sleep instruction.

7. The apparatus of claim 1, wherein the sleep instruction is detected at an instruction decode stage of the instruction pipeline.

8. The apparatus of claim 7, wherein the power control logic instructs the instruction pipeline to cease fetching new instructions after encountering the sleep instruction at the decode stage.

9. The apparatus of claim 1, wherein the processor and the power control logic are utilized as part of a media access control (MAC) layer for the wireless communication device.

10. A method comprising:

detecting a sleep instruction in a power control logic associated with a processor for a wireless communication device, in which the processor includes an instruction pipeline for executing instructions;

stopping fetch of new instructions after encountering the sleep instruction;

completing any preceding instruction or instructions still in the instruction pipeline in response to the sleep instruction;

placing the processor in a low-power state after completing any preceding instruction or instructions still in the instruction pipeline;

reactivating the instruction pipeline to process a subsequent instruction following the sleep instruction in response to a wake-up signal; and

performing processing tasks associated with the subsequent instruction following the sleep instruction in response to the wake-up signal.

11. The method of claim 10, further comprising executing the sleep instruction in the instruction pipeline that comprises a programmable state machine.

12. The method of claim 10, further comprising generating the wake-up signal by a logical OR'"'"'ing of multiple wake-up conditions.

13. The method of claim 10, further comprising generating the wake-up signal by a logical OR'"'"'ing of multiple wake-up conditions and a time-out interval.

14. The method of claim 13, further comprising storing in a register the wake-up conditions and the time-out interval.

15. The method of claim 10, wherein the detecting the sleep instruction includes using a decode logic to detect the sleep instruction.

16. The method of claim 10, wherein the detecting the sleep instruction is performed at an instruction decode stage of the instruction pipeline.

17. The method of claim 10, wherein the processor and the power control logic are utilized as part of a media access control (MAC) layer for the wireless communication device.