Power source network analyzing apparatus, power source network analyzing method, and power source network analyzing program

• US 20090299718A1
• Filed: 01/22/2009
• Published: 12/03/2009
• Est. Priority Date: 05/29/2008
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Amano, Yasuo
• Granted Patent: US 8,249,849 B2
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

An area partitioning processing unit equally partitions a power source network analysis object area of an LSI according to the number or size of partitioned areas specified by a user or partitions the power source network analysis object area according to the user'"'"'s specification. A border processing unit extracts and adds a range-of-influence part of the power source network that can electrically influence a border between the partitioned area partitioned by the area partitioning processing unit and an adjacent power source network area. A modeling processing unit performs processing of resistance modeling of the partitioned area or a correction spot with the range-of-influence part added thereto by the border processing unit. A power source network analyzing processing unit analyzes a resistance model modeled by the modeling processing unit and calculates potential of each via as a current source to a load element.

Claims

1. A power source network analyzing apparatus comprising:

an analysis object area partitioning processing unit that, based on design information of an integrated circuit, partitions a power source network analysis object area of the integrated circuit into partitioned power source network analysis object areas;

an adjacent border area extracting and adding processing unit that extracts a border adjacent area electrically influencing the partitioned power source network analysis object area partitioned by the analysis object area partitioning processing unit and adds the border adjacent area to the partitioned power source network analysis object area;

a resistance model generating processing unit that generates a resistance model of the partitioned power source network analysis object area with the border adjacent area added thereto by the adjacent border area extracting and adding processing unit; and

a power source network analyzing processing unit that performs power source network analyzing processing on the resistance model generated by the resistance model generating processing unit.

2. The power source network analyzing apparatus according to claim 1, wherein

the analysis object area partitioning processing unit equally partitions the power source network analysis object area of the integrated circuit into the partitioned power source network analysis object areas, based on the number of partitions or a partition size specified by a user.

3. The power source network analyzing apparatus according to claim 1, wherein

the adjacent border area extracting and adding processing unit extracts the border adjacent area by extracting a current source and/or a power supplying source that electrically influences the partitioned power source network analysis object area partitioned by the analysis object area partitioning processing unit.

4. The power source network analyzing apparatus according to claim 1, further comprising:

a border adjacent area analysis result removing processing unit that removes the border adjacent area from results of the analysis of the resistance model by the power source network analyzing processing unit; and

a power source network analysis result integrating processing unit that integrates the results of the analysis of the resistance model after removal by the border adjacent area analysis result removing processing unit into results of the power source network analysis of the power source network analysis object area as a whole of the integrated circuit.

5. The power source network analyzing apparatus according to claim 4, further comprising:

an applied voltage determining processing unit that determines whether a voltage is normal that is applied to a load element in the power source network analysis object area, based on the results of the power source network analysis of the power source network analysis object area as a whole of the integrated circuit integrated by the power source network analysis result integrating processing unit.

6. The power source network analyzing apparatus according to claim 5, further comprising:

a notifying unit of notifying a computer design support device that supports design of the integrated circuit of results of determination of whether the voltage is normal that is applied to the load element in the power source network analysis object area by the applied voltage determining processing unit.

7. A power source network analyzing method comprising:

partitioning, based on design information of an integrated circuit, a power source network analysis object area of the integrated circuit into partitioned power source network analysis object areas;

extracting a border adjacent area electrically influencing the partitioned power source network analysis object area;

adding the border adjacent area to the partitioned power source network analysis object area;

generating a resistance model of the partitioned power source network analysis object area with the border adjacent area added thereto; and

performing power source network analyzing processing on the generated resistance model.

8. The power source network analyzing method according to claim 7, further comprising

equally partitioning the power source network analysis object area of the integrated circuit into the partitioned power source network analysis object areas, based on the number of partitions or a partition size specified by a user.

9. The power source network analyzing method according to claim 7, further comprising

extracting the border adjacent area by extracting a current source and/or a power supplying source that electrically influences the partitioned power source network analysis object area.

10. The power source network analyzing method according to claim 7, further comprising:

removing the border adjacent area from results of the analysis of the resistance model; and

integrating the results of the analysis of the resistance model after the removing into results of the power source network analysis of the power source network analysis object area as a whole of the integrated circuit.

11. The power source network analyzing method according to claim 10, further comprising:

determining whether a voltage is normal that is applied to a load element in the power source network analysis object area, based on the results of the power source network analysis of the power source network analysis object area as a whole of the integrated circuit after the integrating.

12. The power source network analyzing method according to claim 11, further comprising:

notifying a computer design support device that supports design of the integrated circuit of results of determination of whether the voltage is normal that is applied to the load element in the power source network analysis object area.

13. A power source network analyzing program product including a computer-readable recording medium that stores therein a computer program that causes a computer to execute:

partitioning, based on design information of an integrated circuit, a power source network analysis object area of the integrated circuit into partitioned power source network analysis object areas;

extracting a border adjacent area electrically influencing the partitioned power source network analysis object area;

adding the border adjacent area to the partitioned power source network analysis object area;

generating a resistance model of the partitioned power source network analysis object area with the border adjacent area added thereto; and

performing power source network analyzing processing on the generated resistance model.

14. The power source network analyzing program product according to claim 13, further comprising

equally partitioning the power source network analysis object area of the integrated circuit into the partitioned power source network analysis object areas, based on the number of partitions or a partition size specified by a user.

15. The power source network analyzing program product according to claim 13, further comprising

extracting the border adjacent area by extracting a current source and/or a power supplying source that electrically influences the partitioned power source network analysis object area.

16. The power source network analyzing program product according to claim 13, further comprising:

removing the border adjacent area from results of the analysis of the resistance model; and

integrating the results of the analysis of the resistance model after the removing into results of the power source network analysis of the power source network analysis object area as a whole of the integrated circuit.

17. The power source network analyzing program product according to claim 16, further comprising:

determining whether a voltage is normal that is applied to a load element in the power source network analysis object area, based on the results of the power source network analysis of the power source network analysis object area as a whole of the integrated circuit after the integrating.

18. The power source network analyzing program product according to claim 17, further comprising:

notifying a computer design support device that supports design of the integrated circuit of results of determination of whether the voltage is normal that is applied to the load element in the power source network analysis object area.