SSD WITH DISTRIBUTED PROCESSORS

• US 20090300274A1
• Filed: 05/19/2009
• Published: 12/03/2009
• Est. Priority Date: 05/27/2008
• Status: Active Grant

• Current Assignee: Hangzhou Hualan Microelectronique Co., Ltd.
• Original Assignee: Initio Corporation (Hangzhou Hualan Microelectronique Co., Ltd.)
• Inventors: TSU, ChuanJen, LUO, Jianjun
• Granted Patent: US 8,244,961 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.

Claims

1. A solid state drive, comprising:

a first serial data bus configured to be coupled to a corresponding serial data bus of a host device;

one or more flash processor units (FPUs) coupled to the first serial data bus, each of the one or more FPUs configured to manage at least one respective group of flash memory units; and

a supervisor processing unit in data communication with each of the one or more FPUs, the supervisor processing unit configured to manage data transfer between the host and each of the FPUs.

2. The solid state drive of claim 1, wherein each of the FPUs is configured to perform an error correction coding on data received from the at least one respective group of flash memory units.

3. The solid state drive of claim 1, wherein each of the FPUs is configured to perform wear-leveling for the at least one respective group of flash memory units.

4. The solid state drive of claim 1, wherein each of the FPUs is configured to perform bad block management for the at least one respective group of flash memory units.

5. The solid state drive of claim 1, wherein the controller includes at least two FPUs, one of the FPUs coupled to a group of single-level cell (SLC) flash units.

6. The solid state drive of claim 5, wherein at least one of the one or more flash processor units is coupled to a group of multi-level cell (MLC) flash units and multi-level cell (MLC) flash units.

7. The solid state drive of claim 1, wherein the controller includes at two FPUs, one of the FPUs coupled to a group of multi-level cell (MLC) flash units.

8. The solid state drive of claim 1, wherein the flash group includes a combination of single-level cell (SLC) flash units and multi-level cell (MLC flash units.

9. An integrated circuit chip, comprising:

a first serial data bus disposed on the integrated circuit chip and configured to be coupled to a corresponding serial data bus of a host device;

a plurality of flash processing units (FPUs) disposed on the integrated circuit chip in data communication with the first serial data bus, each of the FPUs configured to manage data transfer to and from a respective group of flash memory units; and

a supervisor processing unit disposed on the integrated circuit chip and in data communication with the first serial data bus and each of the plurality of FPUs, the supervisor processing unit configured to manage access to the first serial data bus by each of the FPUs.

10. The integrated circuit of claim 9, wherein the first serial data bus is a serial advanced technology attachment (SATA) channel.

11. The integrated circuit of claim 9, wherein the first serial data bus is a universal serial bus (USB) channel.

12. The integrated circuit of claim 9, wherein each of the FPUs includes a flash interface having logic configured to select and deselect a flash memory unit of the respective group of flash memory units.

13. The integrated circuit of claim 9, wherein each of the plurality of FPUs is configured to perform an error correction coding for the respective groups of flash memory units.

14. The integrated circuit of claim 9, wherein each of the plurality of FPUs is configured to perform wear-leveling for the respective group of flash memory units.

15. The integrated circuit of claim 9, wherein each of the plurality of FPUs is configured to perform bad block management for the respective group of flash memory units.

16. The integrated circuit of claim 9, wherein each of the plurality of FPUs include:

a microprocessing unit having a processing capability that is less than a processing capability of the supervisor processing unit; and

an error correction code (ECC) engine connected to the microprocessing unit for performing error correction.

17. A system, comprising:

a first serial data bus configured to be coupled to a corresponding serial data bus of a host device;

a plurality of processors of a first type, each of the plurality of processors of the first type coupled to the first serial bus and a respective flash memory device, and

a processor of a second type configured to manage access by the plurality of processors of the first type to the first serial data bus.

18. The system of claim 17, wherein each of the plurality of processors of the first type are configured to perform wear-leveling for the respective memory device to which it is coupled.

19. The system of claim 17, wherein each of the plurality of processors of the first type are configured to execute an error correction code for the respective memory device to which it is coupled.

20. The system of claim 17, wherein the first serial data bus is a serial advanced technology attachment (SATA) channel.

21. The system of claim 17, wherein the first serial data bus is a universal serial bus (USB) channel.

22. The system of claim 17, wherein at least one of the flash memory devices includes multi-level cell flash.

23. The system of claim 22, wherein at least one of the flash memory devices includes single-level cell flash.

24. The system of claim 17, wherein at least one of the flash memory devices includes single-level cell flash.