MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING READ DATA
First Claim
Patent Images
1. A memory system comprising:
- a plurality of memory devices, each including a respective array of memory cells, each of the plurality of memory devices configured to access data from a respective array of memory cells in response to capturing a respective read command, each memory device further configured to capture the respective read command at least partially responsive to an array access signal and output the respective read data corresponding to the respective read command responsive to a respective output control signal;
an interface coupled to each of the plurality of memory devices, the interface configured to receive the respective read data output from each of the plurality of memory devices; and
a controller operating according to a controller clock signal having a controller clock period coupled to the plurality of memory devices through the interface, the controller configured to transmit the respective read commands to the plurality of memory devices, the controller further configured to transmit the array access signal to the plurality of memory devices and transmit the respective output control signal for each of the plurality of memory devices, at least partially responsive to transmitting first and second consecutive read commands to two different ones of the plurality of memory devices, the controller configured to delay a time when read data corresponding to the second consecutive read command is transmitted on the interface by less than one controller clock period.
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Abstract
Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.
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Citations
23 Claims
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1. A memory system comprising:
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a plurality of memory devices, each including a respective array of memory cells, each of the plurality of memory devices configured to access data from a respective array of memory cells in response to capturing a respective read command, each memory device further configured to capture the respective read command at least partially responsive to an array access signal and output the respective read data corresponding to the respective read command responsive to a respective output control signal; an interface coupled to each of the plurality of memory devices, the interface configured to receive the respective read data output from each of the plurality of memory devices; and a controller operating according to a controller clock signal having a controller clock period coupled to the plurality of memory devices through the interface, the controller configured to transmit the respective read commands to the plurality of memory devices, the controller further configured to transmit the array access signal to the plurality of memory devices and transmit the respective output control signal for each of the plurality of memory devices, at least partially responsive to transmitting first and second consecutive read commands to two different ones of the plurality of memory devices, the controller configured to delay a time when read data corresponding to the second consecutive read command is transmitted on the interface by less than one controller clock period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A processor-based system comprising:
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a processor configured to generate read commands; a memory system coupled to the processor, the memory system comprising; a plurality of memory devices, each including a respective array of memory cells, each of the plurality of memory devices configured to access data from a respective array of memory cells in response to capturing a respective read command, each memory device further configured to capture the respective read command responsive to an array access signal and output the respective read data corresponding to the respective read command at least partially responsive to a respective output control signal; an interface coupled to each of the plurality of memory devices, the interface configured to receive the respective read data output from each of the plurality of memory devices; and a controller operating according to a controller clock signal having a controller clock period coupled to the plurality of memory devices through the interface, the controller configured to transmit the respective read commands to the plurality of memory devices, the controller further configured to transmit the array access signal to the plurality of memory devices and transmit the respective output control signal for each of the plurality of memory devices, at least partially responsive to transmitting first and second consecutive read commands to two different ones of the plurality of memory devices, the controller configured to delay a time when read data corresponding to the second consecutive read command is transmitted on the interface by less than one controller clock period.
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16. A memory device comprising:
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an array of memory cells; a capture circuit having an input terminal, an output terminal, and a control terminal, the capture circuit configured to receive a read command at the input terminal, the capture circuit further configured to receive an array access signal at the control terminal and capture the read command responsive to the array access signal; a delay circuit coupled to the capture circuit, the delay circuit having an input terminal, an output terminal and a control terminal, the delay circuit configured to receive the read command and delay the read command responsive to a delay control signal received at the delay circuit control terminal; an access circuit coupled to the delay circuit, the access circuit operable to access the array of memory cells at a location corresponding to the read command such that read data is output from the array of memory cells; and a buffer memory coupled to the array of memory cells and configured to receive data output from the array of memory cells, the buffer memory configured to receive a an output control signal and output the read data responsive to the output control signal. - View Dependent Claims (17, 18)
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19. A method comprising:
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receiving a controller clock signal having a controller clock period; receiving a plurality of read commands including a first and second consecutive read command corresponding to different memory devices sharing an interface for transmission of read data; transmitting the first read command to a first corresponding memory device in a first controller clock period; transmitting a first output control signal to the first corresponding memory device a certain time after transmitting the first read command, the first corresponding memory device configured to place the read data on the interface responsive to the strobe signal; transmitting the second read command to the second corresponding memory device after a delay time of at least one unit time interval and less than one controller clock cycle; and transmitting a second output control signal to the second corresponding memory device the certain time after transmitting the second read command, the second corresponding memory device configured to transmit the read data on the interface responsive to the second output control signal.
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20. A method comprising:
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receiving a controller clock signal having a controller clock period; transmitting a first read command to a first corresponding memory device in a first controller clock period; transmitting a first output control signal to the first corresponding memory device a certain time after transmitting the first read command, the first corresponding memory device configured to place read data on the interface responsive to the first output control signal; transmitting a second consecutive read command to a second corresponding memory device different than the first memory device in a second consecutive controller clock period; and transmitting a second output control signal to the second corresponding memory device the certain time plus a delay time after transmitting the second read command, the second corresponding memory device configured to place read data on the interface responsive to the second output control signal. - View Dependent Claims (21, 22)
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23. A method comprising:
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receiving a controller clock signal having a controller clock period; issuing a plurality of read commands having a first memory device transition including two consecutive read commands directed to different memory devices sharing an interface for transmission of data; transmitting a first read command of the first memory device transition to the corresponding memory device in a first controller clock period; transmitting a first array access signal to the corresponding memory device in the first controller clock period, the array access signal having a rising edge and a falling edge, the corresponding memory device configured to capture the first read command and begin accessing a corresponding memory array responsive to the rising edge of the first array signal; transmitting a first output control signal to the first corresponding memory device a certain time after transmitting the rising edge of the first array access signal, the first corresponding memory device configured to place read data on the interface responsive to the first output control signal; transmitting the second read command of the first memory device transition to the corresponding memory device in a second consecutive controller clock period; transmitting a second array access signal to the corresponding memory device in the second controller clock period, the second array access signal having a rising edge and a falling edge and transmitting a delay control signal to the corresponding memory device, the corresponding memory device configured, responsive to the delay control signal, to capture the second read command on the rising edge of the second array cycle pulse; delay access to the corresponding memory array until at least the falling edge of the second array access signal; and transmitting a second output control signal to the second corresponding memory device the certain time after transmitting the falling edge of the second array access signal, the second corresponding memory device configured to place read data on the interface responsive to the second output control signal.
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Specification