PROCESSING SYSTEM WITH LINKED-LIST BASED PREFETCH BUFFER AND METHODS FOR USE THEREWITH

• US 20090300320A1
• Filed: 05/28/2008
• Published: 12/03/2009
• Est. Priority Date: 05/28/2008
• Status: Active Grant

• Current Assignee: VIXS Systems Incorporated (Pixelworks Incorporated)
• Original Assignee: VIXS Systems Incorporated (Pixelworks Incorporated)
• Inventors: Zhang, Jing
• Granted Patent: US 8,650,364 B2
• Time in Patent Office: Days
• US Class Current: 711/213
• CPC Class Codes: G06F 12/0862 with prefetch

Abstract

A processing device includes a memory and a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory. A prefetch memory interface prefetches prefetch data to a prefetch buffer, retrieves the read data from the prefetch buffer when the read data is included in the prefetch buffer, and retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein the prefetch buffer is managed via a linked list.

Claims

1. A video processing system for producing a processed video signal from a video signal, the video processing device comprising:

a memory;

a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory;

a prefetch memory interface coupled to the processor and the memory, that prefetches prefetch data to a prefetch buffer, that retrieves the read data from the prefetch buffer when the read data is included in the prefetch buffer, and that retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein the prefetch buffer is managed via a linked list.

2. The video processing system of claim 1 wherein the prefetch buffer includes a plurality of entries that are linked via the linked list.

3. The video processing system of claim 2 wherein the plurality of entries are divided into a set of allocated entries and a set of free entries.

4. The video processing system of claim 2 wherein each of the plurality of entries includes a status field that indicates a prefetch status of the entry.

5. The video processing system of claim 2 wherein each of the plurality of entries includes a linked list pointer that indicates a neighboring entry in the linked list.

6. The video processing system of claim 2 wherein each of the plurality of entries includes a tag that indicates the identity of the prefetch data.

7. The video processing system of claim 1 wherein the prefetch memory interface includes a prefetch request generator that selects prefetch data based on a programmable prefetch window.

8. A processing system comprising:

a memory;

a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory;

a prefetch memory interface coupled to the processor and the memory, that prefetches prefetch data to a prefetch buffer, that retrieves the read data from the prefetch buffer when the read data is included in the prefetch buffer, and that retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein the prefetch buffer is managed via a linked list.

9. The processing system of claim 8 wherein the prefetch buffer includes a plurality of entries that are linked via the linked list.

10. The processing system of claim 9 wherein the plurality of entries are divided into a set of allocated entries and a set of free entries.

11. The processing system of claim 9 wherein each of the plurality of entries includes a status field that indicates a prefetch status of the entry.

12. The processing system of claim 9 wherein each of the plurality of entries includes a linked list pointer that indicates a neighboring entry in the linked list.

13. The processing system of claim 9 wherein each of the plurality of entries includes a tag that indicates the identity of the prefetch data.

14. The processing system of claim 8 wherein the prefetch memory interface includes a prefetch request generator that selects prefetch data based on a programmable prefetch window.

15. A method comprising:

generating a plurality of read commands for reading read data from a memory;

prefetching prefetch data to a prefetch buffer;

managing the prefetch buffer via a linked list;

retrieving the read data from the prefetch buffer when the read data is included in the prefetch buffer; and

retrieving the read data from the memory when the read data is not included in the prefetch buffer.

16. The method of claim 15 wherein the prefetch buffer includes a plurality of entries that are linked via the linked list.

17. The method of claim 16 wherein the plurality of entries are divided into a set of allocated entries and a set of free entries.

18. The method of claim 16 wherein each of the plurality of entries includes a status field that indicates a prefetch status of the entry.

19. The method of claim 16 wherein each of the plurality of entries includes a linked list pointer that indicates a neighboring entry in the linked list.

20. The method of claim 16 wherein each of the plurality of entries includes a tag that indicates the identity of the prefetch data.

21. The method of claim 15 wherein prefetching the prefetch data includes selecting the prefetch data based on a programmable prefetch window.

22. A processing device comprising:

a memory;

a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory;

a prefetch memory interface coupled to the processor and the memory, that prefetches prefetch data to a prefetch buffer, that retrieves the read data from the prefetch buffer when the read data is included in the prefetch buffer, and that retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein a plurality of entries in the prefetch buffer are managed via state transition among a plurality of entry states.

23. The processing system of claim 22 wherein the prefetch memory interface includes a tag and buffer server that centrally manages the entries in the prefetch buffer.

24. The processing system of claim 22 wherein each of the plurality of entries includes a status field that indicates one of the plurality of entry states.

25. The processing system of claim 22 wherein the plurality of entries are linked via a linked list.

26. The processing system of claim 25 wherein each of the plurality of entries includes a linked list pointer that indicates a neighboring entry in the linked list.

27. The processing system of claim 22 wherein each of the plurality of entries includes a tag that indicates the identity of the prefetch data.

28. The processing system of claim 22 wherein the prefetch memory interface includes a prefetch request generator that selects prefetch data based on a programmable prefetch window.