DATA PROCESSING SYSTEM, APPARATUS AND METHOD FOR PERFORMING FRACTIONAL MULTIPLY OPERATIONS

• US 20090300325A1
• Filed: 08/12/2009
• Published: 12/03/2009
• Est. Priority Date: 08/09/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Aldrich, Bradley C., Paver, Nigel C.
• Granted Patent: US 8,131,981 B2
• Time in Patent Office: Days
• US Class Current: 712/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for the fractional multiply operations. A coprocessor included in the processing core performs the fractional multiply operations on the operands and stores the result in a destination register that is also included in the processing core.

Claims

1. A method comprising:

decoding a fractional multiply operation that specifies a first operand and a second operand both stored in a first source register, and a third operand and a forth operand both stored in a second source register;

executing a first multiply operation on the first and third operands pursuant to the fractional multiply operation to generate a first intermediate product;

executing a second multiply operation on the second and fourth operands pursuant to the fractional multiply operation to generate a second intermediate product;

shifting the first intermediate product and the second intermediate by a predetermined number of bit positions; and

storing the shifted first and second intermediate products in a destination register.

2. The method according to claim 1, further comprising:

rounding the first intermediate product and the second intermediate product before the shifting by adding a rounding value to the first intermediate product and to the second intermediate product when the fractional multiply operation specifies that a rounding should be performed.

3. The method according to claim 2, wherein the first, second, third and fourth operands are each 32-bit operands, and the predetermined number of bit positions in the shifting is 31.

4. The method according to claim 2, wherein the first, second, third and fourth operands are each 16-bit operands and the predetermined number of bit positions in the shifting is 15.

5. The method according to claim 4, wherein the fractional multiply operation specifies a fifth operand and a sixth operand both stored in the first source register, and a seventh operand and an eighth operand both stored in the second source register, the method further comprising:

executing a third multiply operation on the fifth and seventh operands to generate a third intermediate product;

executing a fourth multiply operation on the sixth and eighth operands to generate a fourth intermediate product;

rounding the third and fourth intermediate products by adding a rounding value to the third intermediate product and to the fourth intermediate product when the fractional multiply operation specifies that another rounding should be performed;

shifting the third intermediate product and the fourth intermediate product by the predetermined number of bit positions; and

storing the shifted third and fourth intermediate products in the destination register.

6. The method according to claim 2, further comprising:

saturating the shifted first and second intermediate products to n-bit values before the storing, wherein n is specified by the fractional multiply operation.

7. The method according to claim 6, further comprising:

storing saturation history in a saturation status flag register according to which of the first and second intermediate products saturate.

8. An apparatus comprising:

a coprocessor interface unit that is configured to identify an instruction for a fractional multiply operation, the fractional multiply operation specifying a first operand, a second operand, a third operand and a fourth operand;

a register file unit; and

an execution unit that is configured to perform the fractional multiply operation by;

executing a first multiply operation on the first and third operands pursuant to the fractional multiply operation to generate a first intermediate product;

executing a second multiply operation on the second and fourth operands pursuant to the fractional multiply operation to generate a second intermediate product;

shifting the first intermediate product and the second intermediate product by a predetermined number of bit positions; and

storing the shifted first and second intermediate products in a destination register of the register file unit.

9. The apparatus according to claim 8, wherein the execution unit performs the fractional multiply operation by rounding the first intermediate product and the second intermediate product, before shifting the first intermediate product and the second intermediate product, by adding a rounding value to the first intermediate product and to the second intermediate product when the fractional multiply operation specifies that a rounding should be performed.

10. The apparatus according to claim 9, wherein the first, second, third and fourth operands are each 32-bit operands, and the predetermined number of bit positions in the shifting is 31.

11. The apparatus according to claim 9, wherein the first, second, third and fourth operands are each 16-bit operands, and the predetermined number of bit positions in the shifting is 15.

12. The apparatus according to claim 11, wherein

the fractional multiply operation identifies a fifth operand, a sixth operand, a seventh operand and an eighth operand, and

the execution unit performs the fractional multiply operation by:

executing a third multiply operation on the fifth and seventh operands to generate a third intermediate product;

executing a fourth multiply operation on the sixth and eighth operands to generate a fourth intermediate product;

rounding the third and fourth intermediate products by adding a rounding value to the third intermediate product and to the fourth intermediate product when the fractional multiply operation specifies that a rounding should be performed;

shifting the third intermediate product and the fourth intermediate product by the predetermined number of bit positions; and

storing the shifted third and fourth intermediate products in the destination register.

13. The apparatus according to claim 9, wherein the execution unit performs the fractional multiply operation by:

saturating the shifted first and second intermediate products to n-bit values before the storing, wherein n is specified by the fractional multiply operation; and

storing saturation history in a saturation status flag register of the register file unit according to which of the first and second intermediate products saturate.

14. A data processing system comprising:

an addressable memory to store a plurality of instructions including instructions for SIMD operations; and

a processing core including;

an execution core that is configured to access a fractional multiply instruction for a SIMD fractional multiply operation stored by the addressable memory;

a first source register to store a first operand and a second operand;

a second source register to store a third operand and a fourth operand;

a destination register; and

a coprocessor that is configured to perform the SIMD fractional multiply operation by;

executing a first multiply operation on the first and third operands pursuant to the SIMD fractional multiply operation to generate a first intermediate product;

executing a second multiply operation on the second and fourth operands pursuant to the SIMD fractional multiply operation to generate a second intermediate product;

shifting the first intermediate product and the second intermediate product by a predetermined number of bit positions; and

storing the shifted first and second intermediate products in the destination register.

15. The data processing system according to claim 14, further comprising:

a wireless interface to receive a digital data signal; and

an I/O system to provide at least the first and second operands to the processing core from the digital data signal.

16. The data processing system according to claim 14, wherein the coprocessor performs the SIMD fractional multiply operation by rounding the first intermediate product and the second intermediate product before the shifting by adding a rounding value to the first intermediate product and to the second intermediate product when the SIMD fractional multiply operation specifies that a rounding should be performed.

17. The data processing system according to claim 16, wherein the first, second, third and fourth operands are each 32-bit operands, and the predetermined number of bit positions in the shifting is 31.

18. The data processing system according to claim 16, wherein the first, second, third and fourth operands are each 16-bit operands, and the predetermined number of bit positions in the shifting is 15.

19. The data processing system according to claim 18, wherein

the first source register stores a fifth operand and a sixth operand,

the second source register stores a seventh operand and an eighth operand, and

the coprocessor performs the SIMD fractional multiply operation by:

executing a third multiply operation on the fifth and seventh operands to generate a third intermediate product;

executing a fourth multiply operation on the sixth and eighth operands to generate a fourth intermediate product;

rounding the third and fourth intermediate products by adding a rounding value to the third intermediate product and to the fourth intermediate product when the SIMD fractional multiply operation specifies that another rounding should be performed;

shifting the third intermediate product and the fourth intermediate product by the predetermined number of bit positions; and

storing the shifted third and fourth intermediate products in the destination register.

20. The data processing system according to claim 14, the processing core further including a saturation status flag register, wherein

the execution unit performs the fractional multiply operation by:

saturating the shifted first and second intermediate products to n-bit values before the storing, wherein n is specified by the SIMD fractional multiply operation; and

storing saturation history in the saturation status flag register according to which of the first and second intermediate products saturate.