HIGH SPEED NETWORK INTERFACE WITH AUTOMATIC POWER MANAGEMENT WITH AUTO-NEGOTIATION

• US 20090300392A1
• Filed: 07/20/2009
• Published: 12/03/2009
• Est. Priority Date: 08/29/2001
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Wang, Chi-Lie, Henderson, Nathan, Hu, Baodong
• Granted Patent: US 8,046,614 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A computer system comprises host processor and a network interface, wherein the host processor includes resources supporting a full power mode, a lower power mode and a power down mode, as seen in standard system bus specifications such as PCI and InfiniBand. The network interface includes a medium interface unit coupled to network media supporting a least high speed protocol, such as a Gigabit Ethernet or high-speed InfiniBand, and a lower speed protocol, such as one of 10 Mb and 100 Mb Ethernet or a lower speed InfiniBand. Power management circuitry forces the medium interface unit to the lower speed protocol in response to an event signaling entry of the lower power mode. In the lower power mode, the network interface consumes less than the specified power when executing the lower speed protocol, and consumes greater than the specified power when executing the high speed protocol. Logic in the network interface operates in the lower power mode, and uses the lower speed protocol to detect a pattern in incoming packets. In response to the detection of said pattern, the logic issues a reset signal to the host processor. Thus, the network interface operates as a wake-up device in the lower power mode, using the lower speed protocol.

Claims

1-27. -27. (canceled)

28. In an integrated circuit containing both a main processing module and a networking interface module having a full power mode, a lower power mode and a power off mode, and supporting a plurality of protocols including a high speed protocol and a lower speed protocol, a method of power management, comprising:

receiving a command at a state machine indicating a sleep state is desired;

sending control signals from the state machine to a medium interface unit to initiate negotiation of a low speed protocol from a high speed protocol;

suppressing a link-change signal at a wake-up detector; and

,

entering a sleep state at the state machine where the network interface module operates in a low power mode.

29. The method of claim 28, wherein the integrated circuit consumes less than a specified power for said lower power mode when executing said lower speed protocol, and consumers greater than the specified power when executing said high speed protocol.

30. The method of claim 28, wherein the integrated circuit consumes less than a specified power of about 1.3 Watts for said lower power mode when executing said lower speed protocol, and consumes greater than the specified power when executing said high speed protocol.

31. The method of claim 28, including using the lower speed protocol in the lower power mode to detect a pattern in incoming packets, and in response to detection of said pattern, to issue a reset signal to the main processing module.

32. The method of claim 28, including providing resources on the integrated circuit for formatting packets according to protocols compliant with 10 Megabit, 100 Megabit and Gigabit Ethernet protocol standards, and wherein said high speed protocol is Gigabit Ethernet, and said lower speed protocol is one of 10 Megabit Ethernet and 100 megabit Ethernet.

33. The method of claim 28, including providing resources on the network interface module for formatting packets according to a protocol compliant with an InfiniBand protocol standard, and wherein said higher speed protocol is InfiniBand.

34. The method of claim 28, wherein said main processing module monitors the network interface module for a wake up event involving a loss of link or a change of link on the network interface, and including blocking signals indicating said wake up event for a time interval while forcing the network processing module to change to the lower speed protocol.

35. An integrated circuit comprising:

a main processing module,

a network processing module, whereas the network processing module comprises a port that transmits data to a network and a medium interface unit coupled to network media supporting at least a high speed protocol and a lower speed protocol;

a memory that stores data packets in transit between the main processing module and the network; and

power management logic on the integrated circuit comprising a state machine having a full power state, a low power state, and a power down state, configured to cause the medium interface unit to renegotiate from the high speed protocol to the lower speed protocol in response to an event signaling entry to the lower power mode and to cause the medium interface unit to enter a power down mode if the lower speed protocol is not successfully renegotiated.

36. The integrated circuit of claim 35, wherein the port, memory and medium interface unit when executing said lower speed protocol consume less than a specified power for said lower power mode, and consume greater than the specified power when executing said high speed protocol.

37. The integrated circuit of claim 35, wherein the first port, second port, memory and medium interface unit when executing said lower speed protocol consume less than a specified power of about 1.3 Watts for said lower power mode, and the consume greater than the specified power when executing said high speed protocol.

38. The integrated circuit of claim 35, including logic operating in said lower power mode using the lower speed protocol to detect a pattern in incoming packets, and in response to detection of said pattern, to issue a reset signal to the main processing module.

39. The integrated circuit of claim 35, wherein the medium interface unit comprises circuitry for formatting packets according to protocols compliant with 10 Megabit, 100 Megabit and Gigabit Ethernet protocol standards, and wherein said high speed protocol is Gigabit Ethernet, and said lower speed protocol is one of 10 Megabit Ethernet and 100 megabit Ethernet.

40. The integrated circuit of claim 35, wherein the medium interface unit comprises circuitry for formatting packets according to a protocol compliant with an InfiniBand protocol standard, and wherein said high speed protocol is InfiniBand.

41. The integrated circuit of claim 35, including logic to generate indications of a wake up event involving a loss of link or a change of link, and wherein said power management logic blocks signals indicating said wake up event for a time interval during which the power management logic forces the medium interface unit to the lower speed protocol.

42. The integrated circuit of claim 35, wherein said event signaling entry into the lower power mode is a signal generated by the main processing module.

43. The integrated circuit of claim 35, wherein said integrated circuit includes power detection circuit adapted for connection to a system power supply, and said event detected by the voltage detector signaling entry into the lower power mode comprises a loss of power from the system power supply.