METHOD, APPARATUS AND SYSTEM FOR REDUCING POWER CONSUMPTION INVOLVING DATA STORAGE DEVICES

• US 20090300397A1
• Filed: 06/25/2009
• Published: 12/03/2009
• Est. Priority Date: 04/17/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Seaman, Mark J., Nguyen, Lu
• Granted Patent: US 8,291,245 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

The invention provides a method, apparatus and system for reducing power consumption involving data storage devices. One embodiment involves storing data in a first memory; in response to the first memory exceeding a first threshold, migrating the data from the first memory to a second memory; in response to the second memory exceeding a second threshold, then activating a third memory if the third memory is in active; and in response to the second memory exceeding a third threshold greater than the second threshold, migrating the data from the second memory to a third memory; wherein the second memory is sized and configured to store data targeted for the third memory to intelligently maintain a portion of the third memory in an inactive state.

Claims

1. A data storage method comprising:

storing data in a first memory;

in response to the first memory exceeding a first threshold, migrating the data from the first memory to a second memory;

in response to the second memory exceeding a second threshold, then activating a third memory if the third memory is inactive;

in response to the second memory exceeding a third threshold greater than the second threshold, migrating the data from the second memory to a third memory; and

wherein the second memory is sized and configured to store data targeted for the third memory to intelligently maintain a portion of the third memory in an inactive state.

2. The method of claim 1 further comprising deactivating the third memory after migrating the data from the second memory to the third memory.

3. The method of claim 2, wherein activating the third memory if the third memory is inactive further includes detecting if a portion of the third memory to store the data into is inactive, and said portion is inactive, then activating said portion of the third memory.

4. The method of claim 1 further comprising:

determining when long sequential data access instructions are occurring;

determining third memory portions that need to be activated for the long sequential access; and

activating the third memory portions necessary for long sequential access, before said third memory portions are actually needed.

5. The method of claim 1 further comprising deactivating the third memory portions after said access.

6. The method of claim 1, further comprising:

in response to a read instruction, determining if requested data is stored in the first memory, the second memory or the third memory; and

in response to the data determined to be stored on the third memory, activating the third memory for access and retrieving the data from the third memory.

7. The method of claim 1, further comprising:

organizing the third memory into a plurality of memory sections;

rearranging a set of data units in the third memory into a plurality of memory groups based on last access time to each data unit, the plurality of memory groups corresponding to said plurality of memory sections such that each memory section contains a group of said data units; and

maintaining a memory section that contains a most recently accessed group of said data units in an active state, and deactivating one or more of the remaining memory sections.

8. An apparatus for reducing power consumption, comprising:

a memory sub-system including;

a first memory;

at least one second memory;

a third memory; and

a controller coupled to the first memory, the second memory and the third memory,

wherein the controller is configured such that;

in response to the first memory exceeding a first threshold, the controller migrates the data from the first memory to the second memory;

in response to the second memory exceeding a second threshold, then the controller activates the third memory if the third memory is inactive; and

in response to the second memory exceeding a third threshold greater than the second threshold, the controller migrates the data from the second memory to the third memory;

wherein the second memory is sized and configured to store data targeted for the third memory to intelligently maintain a portion of the third memory in an inactive state.

9. The apparatus of claim 8, wherein the controller is further configured for deactivating the third memory after migrating the data from the second memory to the third memory.

10. The apparatus of claim 9, wherein the controller is further configured for detecting if a portion of the third memory to store the data into is inactive, and said portion is inactive, then activating said portion of the third memory.

11. The apparatus of claim 8, wherein the controller is further configured for determining when long sequential data access instructions are occurring, determining third memory portions that need to be activated for the long sequential access, and activating the third memory portions necessary for long sequential access, before said third memory portions are actually needed.

12. The apparatus of claim 8, wherein the third memory is divided into a plurality of hierarchical memory groups, wherein a hierarchical memory group n has portions of memory that are accessed more often than a hierarchical memory group n+1, where n is a positive integer, such that hierarchical memory groups other than hierarchical memory group n are powered off until data stored on the other hierarchical memory groups are targeted with an instruction.

13. A distributed data storage system, comprising:

a plurality of processing devices coupled to a plurality of memory sub-system storage devices, each of the memory sub-system storage devices including;

at least one first cache memory device;

at least one second memory device;

a plurality of third memory devices; and

a controller coupled to the first cache memory, the second memory and the third memory,

wherein the controller is configured such that;

in response to the first cache memory exceeding a first threshold, the controller migrates the data from the first cache memory to the second memory;

in response to the second memory exceeding a second threshold, then the controller activates the third memory if the third memory is inactive; and

in response to the second memory exceeding a third threshold greater than the second threshold, the controller migrates the data from the second memory to the third memory;

wherein the second memory is sized and configured to store data targeted for the third memory to intelligently maintain a portion of the third memory in an inactive state.

14. The distributed data storage system of claim 13, wherein the plurality of third memory devices is divided into a plurality of hierarchical accessed memory groups.

15. The distributed data storage system of claim 13, wherein a hierarchical memory group n has portions of memory that are accessed more often than a hierarchical memory group n+1, where n is a positive integer, and hierarchical memory groups other than hierarchical memory group n are powered off until data stored on the other hierarchical memory groups are targeted with an instruction.

16. The distributed data storage system of claim 15, wherein the controller is further configured for deactivating the third memory after migrating the data from the second memory to the third memory.

17. The distributed data storage system of claim 16, wherein the controller is further configured for detecting if a portion of the third memory to store the data into is inactive, and said portion is inactive, then activating said portion of the third memory.

18. The distributed data storage system of claim 15, wherein the controller is further configured for determining when long sequential data access instructions are occurring, determining third memory portions that need to be activated for the long sequential access, and activating the third memory portions necessary for long sequential access, before said third memory portions are actually needed.

19. The distributed data storage system of claim 15, wherein the controller is further configured such that:

in response to a read instruction, the controller determines if requested data is stored in the first cache memory, the second memory or the third memory; and

in response to the data determined to be stored on the third memory, the controller activates the third memory for access and retrieves the data from the third memory.

20. The distributed data storage system of claim 15 wherein:

the third memory is organized into a plurality of memory sections;

a set of data units in the third memory are rearranged into a plurality of memory groups based on last access time to each data unit, the plurality of memory groups corresponding to said plurality of memory sections such that each memory section contains a group of said data units; and

the controller is further configured for maintaining a memory section that contains a most recently accessed group of said data units in an active state, and deactivating one or more of the remaining memory sections.