PRIMARY SIDE CONTROL CIRCUIT AND METHOD FOR ULTRA-LOW IDLE POWER OPERATION

• US 20090300400A1
• Filed: 07/17/2008
• Published: 12/03/2009
• Est. Priority Date: 05/29/2008
• Status: Active Grant

• Current Assignee: iGo, Inc.
• Original Assignee: iGo, Inc.
• Inventors: DuBose, Richard G.
• Granted Patent: US 7,779,278 B2
• Time in Patent Office: Days
• US Class Current: 713/340
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/33523 with galvanic isolation between input and output of both the power stage and the feedback loop

Abstract

A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10^th to 1/1000^th or less of active power is disclosed. An ultra-low idle power supply comprises a primary circuit, a secondary circuit and a control circuit. The control circuit monitors behavior of the primary circuit and determines whether an idle state or no load condition exists, and if so the primary circuit is disengaged. By disengaging the primary circuit, the power consumption of the ultra-low idle power supply is reduced to ultra-low levels.

Claims

1. A power supply configured with an ultra-low idle power mode, said power supply comprising:

a primary circuit configured to receive power from an outside power source;

a secondary circuit coupled to said primary circuit and configured to provide a power output; and

a control circuit configured to monitor said primary circuit and to control said primary circuit such that said primary circuit is substantially disabled when an idle power mode is detected.

2. The power supply of claim 1, wherein said control circuit monitors at least one of a duty cycle, a switching rate or current flowing within said primary circuit to determine whether the power level is above or below a predetermined threshold.

3. The power supply of claim 2, wherein said control circuit comprises a logic control unit configured for monitoring said primary circuit and a power control unit configured for control of said primary circuit.

4. The power supply of claim 3, wherein said logic control unit and said power control unit comprise at least one of a combinational logic machine, a state machine or a microprocessor.

5. The power supply of claim 3, wherein said primary circuit comprises a modulator circuit configured for driving at least one of a transformer or other dielectric isolation device.

6. The power supply of claim 5, wherein said logic control unit is configured to monitor a signal of said modulator circuit.

7. The power supply of claim 5, wherein said power control circuit is configured for control of at least one switch to control said modulator circuit.

8. The power supply of claim 5, wherein said modulator circuit comprises a PWM controller and at least one of a MOSFET or other transistor driver.

9. A circuit configured to facilitate an ultra-low idle power mode in a power supply, said circuit comprising:

an input circuit configured for filtering and rectifying input power;

an energy storage circuit coupled to said input circuit;

a modulator coupled to said energy storage circuit, said modulator configured for modulating the input power at a high frequency rate to drive a transformer and transfer power from a primary side of the transformer to a secondary side of the transformer; and

a control circuit configured to monitor said modulator and to control said primary circuit such that said primary circuit is substantially disabled when said control circuit determines that substantially no load exists such that the power supply is configured in an ultra-low idle power mode.

10. The circuit of claim 9, wherein said control circuit monitors at least one of a duty cycle or switching rate of said modulator to determine whether substantially no load exists.

11. The circuit of claim 9, wherein said control circuit comprises a logic control unit configured for monitoring said modulator and a power control unit configured for control of said circuit.

12. The circuit of claim 9, wherein said modulator comprises a PWM controller and at least one of a MOSFET or other transistor driver.

13. The circuit of claim 11, wherein said logic control unit comprises at least one input coupled to said modulator to monitor an output of said modulator, said output of said modulator comprising at least one of an output pulse rate, a duty cycle and a level of current.

14. The circuit of claim 13, wherein said at least one input coupled to said modulator to monitor at least one of an output pulse rate directly from a PWM controller within said modulator is, an output from an integrator coupled to a PWM controller within said modulator, and an output from an current-to-voltage converter coupled to a PWM controller within said modulator.

15. The circuit of claim 11, wherein said circuit comprises at least one switch device coupled between said power control unit and said modulator, whereby said power control unit opens said at least one switch device to disable said modulator.

16. A method of facilitating a power supply with ultra-low power consumption during idle power operation, said method comprising:

monitoring a characteristic of a primary circuit of said power supply and determining when substantially no load condition exists;

substantially disabling said primary circuit of said power supply when said substantially no load condition is detected to result in an ultra-low power mode.

17. The method according to claim 16, said method further comprising enabling said power supply when said control circuit determines a power load exists.

18. The method of claim 16, wherein said determining when a substantially no load condition exists comprises detecting when at least one of a low duty cycle or switching rate or a current flowing is present within said primary circuit.

19. The method of claim 17, wherein said enabling said power supply occurs when at least one of a duty cycle or switching rate or a current flowing of said primary circuit increases above a threshold level.

20. The method of claim 16, wherein said monitoring comprises having a control circuit monitor at least one of at least one of a duty cycle or switching rate or a current flowing within said primary circuit to determine whether said substantially no load condition exists.

21. The method of claim 20, wherein said control circuit monitors the activity of a modulator to determine whether a substantially no load condition exists.

22. The method of claim 21, wherein said control circuit monitors at least one of an output pulse rate or a duty cycle directly from a PWM controller within said modulator.

23. The method of claim 21, wherein said control circuit monitors an output from an integrator coupled to a PWM controller within said modulator.

24. The method of claim 21, wherein said control circuit monitors an output from a current-to-voltage converter coupled to a PWM controller within said modulator