METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES
First Claim
1. A memory device system, comprising:
- a plurality of stacked memory device die connected to each other through a plurality of conductors, each of the memory device die containing a plurality of memory cells having locations corresponding to respective memory addresses, the memory cells of the memory device die configured for access according to a plurality of vaults;
a logic circuit die on which the memory device die are stacked, the logic circuit die being coupled to the memory device die through a plurality of conductors, the logic circuit die configured to write data to and read date from the memory device die, the logic circuit die including;
a plurality of link interfaces configured to receive serial data and deserialize the data to obtain parallel data;
a plurality of downstream targets, each coupled to a respective one of the plurality of link interfaces and configured to receive the parallel data from the respective link interface, decode command and address portions of the received parallel data;
a switch coupled to the plurality of downstream targets, the switch configured to receive the decoded command and address portions of the received parallel data and couple the decoded command and address portions of the received parallel data to at least one of the plurality of vertical vaults corresponding to the received decoded address portion; and
a packet builder and broadcaster coupled to the plurality of link interfaces, the packet builder and broadcaster including a first input port coupled to receive command signals from a tester on a first interface, and a second input port coupled to receive address signals from the tester on a second interface, the packet builder and broadcaster configured to reformat the command and address signals and to sequentially couple the reformatted command and address signals to at least one of the plurality of link interfaces.
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Accused Products
Abstract
A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.
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Citations
26 Claims
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1. A memory device system, comprising:
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a plurality of stacked memory device die connected to each other through a plurality of conductors, each of the memory device die containing a plurality of memory cells having locations corresponding to respective memory addresses, the memory cells of the memory device die configured for access according to a plurality of vaults; a logic circuit die on which the memory device die are stacked, the logic circuit die being coupled to the memory device die through a plurality of conductors, the logic circuit die configured to write data to and read date from the memory device die, the logic circuit die including; a plurality of link interfaces configured to receive serial data and deserialize the data to obtain parallel data; a plurality of downstream targets, each coupled to a respective one of the plurality of link interfaces and configured to receive the parallel data from the respective link interface, decode command and address portions of the received parallel data; a switch coupled to the plurality of downstream targets, the switch configured to receive the decoded command and address portions of the received parallel data and couple the decoded command and address portions of the received parallel data to at least one of the plurality of vertical vaults corresponding to the received decoded address portion; and a packet builder and broadcaster coupled to the plurality of link interfaces, the packet builder and broadcaster including a first input port coupled to receive command signals from a tester on a first interface, and a second input port coupled to receive address signals from the tester on a second interface, the packet builder and broadcaster configured to reformat the command and address signals and to sequentially couple the reformatted command and address signals to at least one of the plurality of link interfaces. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system, comprising:
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a tester including a first output port, a second output port and a third output port, the tester configured to output command signals at the first output port, address signals at the second output port and output or receive data signals at the third output port; a first interface coupled to the first output port; a second interface coupled to the second output port; a third bi-directional interface coupled to the third output port; and a memory device system comprising; a plurality of stacked memory device die connected to each other through a plurality of conductors, each of the memory device die containing a plurality of memory cells having locations corresponding to respective memory addresses, the memory cells of the memory device die configured for access according to a plurality of vertical vaults; a logic circuit die on which the memory device die are stacked, the logic circuit die being coupled to the memory device die through a plurality of conductors, the logic circuit die configured to write data to and read date from the memory device die, the logic circuit die comprising; a plurality of link interfaces configured to receive serial data and deserialize the data to obtain parallel data; a plurality of downstream targets, each coupled to a respective one of the plurality of link interfaces and configured to receive the parallel data from the respective link interface, decode command and address portions of the received parallel data; a switch coupled to the plurality of downstream targets, the switch configured to receive the decoded command and address portions of the received parallel data and couple the decoded command and address portions of the received parallel data to at least one of the plurality of vertical vaults corresponding to the received decoded address portion; and a packet builder and broadcaster coupled to the plurality of link interfaces, the packet builder and broadcaster including a first input port coupled to receive command signals from a tester on a first interface, and a second input port coupled to receive address signals from the tester on a second interface, the packet builder and broadcaster configured to reformat the command and address signals and to sequentially couple the reformatted command and address signals to at least one of the plurality of link interfaces. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of testing a plurality of stacked memory device die connected to each other and being connected to a logic circuit die on which the memory device die are stacked and being configured for access according to a plurality of vaults, the method comprising:
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receiving at the logic circuit die a write command signal, an address signal and write data from separate interfaces; combining, on the logic circuit die, the command and address signals and at least a portion of the write data into a packet; broadcasting the packet to a plurality of the vaults; writing the write data to a location corresponding to the address in each of the plurality of the vaults; receiving at the logic circuit die a read command signal and an address signal from separate interfaces; combining, on the logic circuit die, the command and address signals into a read packet; broadcasting the read packet to the plurality of the vaults; receiving read data responsive to the read packet from each of the plurality of the vertical vaults; comparing the read data returned from each of the plurality of the vaults; and outputting data to one of the separate interfaces corresponding to the comparison including an indication of whether any of the vaults returned read data different than any of the other plurality of vaults. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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Specification