METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES

• US 20090300444A1
• Filed: 06/03/2008
• Published: 12/03/2009
• Est. Priority Date: 06/03/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Granted Patent: US 7,979,757 B2
• Time in Patent Office: Days
• US Class Current: 714/719
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array

Abstract

A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults.

Claims

1. A memory device system, comprising:

a plurality of stacked memory device die connected to each other through a plurality of conductors, each of the memory device die containing a plurality of memory cells having locations corresponding to respective memory addresses, the memory cells of the memory device die configured for access according to a plurality of vaults;

a logic circuit die on which the memory device die are stacked, the logic circuit die being coupled to the memory device die through a plurality of conductors, the logic circuit die configured to write data to and read date from the memory device die, the logic circuit die including;

a plurality of link interfaces configured to receive serial data and deserialize the data to obtain parallel data;

a plurality of downstream targets, each coupled to a respective one of the plurality of link interfaces and configured to receive the parallel data from the respective link interface, decode command and address portions of the received parallel data;

a switch coupled to the plurality of downstream targets, the switch configured to receive the decoded command and address portions of the received parallel data and couple the decoded command and address portions of the received parallel data to at least one of the plurality of vertical vaults corresponding to the received decoded address portion; and

a packet builder and broadcaster coupled to the plurality of link interfaces, the packet builder and broadcaster including a first input port coupled to receive command signals from a tester on a first interface, and a second input port coupled to receive address signals from the tester on a second interface, the packet builder and broadcaster configured to reformat the command and address signals and to sequentially couple the reformatted command and address signals to at least one of the plurality of link interfaces.

2. The memory device system of claim 1 wherein the packet builder and broadcaster further comprises a third input port coupled to receive data signals from the tester on a third interface, the packet builder and broadcaster further configured to reformat the data signals and sequentially couple the reformatted data signals to the at least one of the plurality of link interfaces.

3. The memory device system of claim 1 wherein the packet builder and broadcaster is further configured to repeat the received command signals to a plurality of the vertical vaults.

4. The memory device system of claim 1 wherein the logic die further comprises:

a packet disassembler and data compare unit configured to receive data from a plurality of vaults, compare the received read data and couple results of the comparison to the tester over the third interface.

5. The memory device system of claim 4 wherein the read data from the plurality of vaults are coupled to the packet disassembler and data compare unit responsive to at least one read command and address coupled to the packet builder and broadcaster.

6. The memory device system of claim 1 further comprising a plurality of vault controllers, each coupled to a respective one of the plurality of vaults and configured to receive command and address signals from the switch and access their respective vault in accordance with the command and address signals.

7. The memory device system of claim 6 wherein the packet builder and broadcaster is configured to direct received command signals to a plurality of the vault controllers.

8. The memory device of claim 1 wherein the third interface is bi-directional and the plurality of link interfaces are bi-directional.

9. The memory device system of claim 1 wherein each of the memory device die comprise a respective dynamic random access memory device die.

10. A system, comprising:

a tester including a first output port, a second output port and a third output port, the tester configured to output command signals at the first output port, address signals at the second output port and output or receive data signals at the third output port;

a first interface coupled to the first output port;

a second interface coupled to the second output port;

a third bi-directional interface coupled to the third output port; and

a memory device system comprising;

a plurality of stacked memory device die connected to each other through a plurality of conductors, each of the memory device die containing a plurality of memory cells having locations corresponding to respective memory addresses, the memory cells of the memory device die configured for access according to a plurality of vertical vaults;

a logic circuit die on which the memory device die are stacked, the logic circuit die being coupled to the memory device die through a plurality of conductors, the logic circuit die configured to write data to and read date from the memory device die, the logic circuit die comprising;

a plurality of link interfaces configured to receive serial data and deserialize the data to obtain parallel data;

a plurality of downstream targets, each coupled to a respective one of the plurality of link interfaces and configured to receive the parallel data from the respective link interface, decode command and address portions of the received parallel data;

a switch coupled to the plurality of downstream targets, the switch configured to receive the decoded command and address portions of the received parallel data and couple the decoded command and address portions of the received parallel data to at least one of the plurality of vertical vaults corresponding to the received decoded address portion; and

a packet builder and broadcaster coupled to the plurality of link interfaces, the packet builder and broadcaster including a first input port coupled to receive command signals from a tester on a first interface, and a second input port coupled to receive address signals from the tester on a second interface, the packet builder and broadcaster configured to reformat the command and address signals and to sequentially couple the reformatted command and address signals to at least one of the plurality of link interfaces.

11. The memory device system of claim 10 wherein the packet builder and broadcaster further comprises a third input port coupled to receive data signals from the tester on the third interface, the packet builder and broadcaster further configured to reformat the data signals and sequentially couple the reformatted data signals to the at least one of the plurality of link interfaces.

12. The memory device system of claim 10 wherein the packet builder and broadcaster is further configured to repeat the received command signals to a plurality of the vertical vaults.

13. The memory device system of claim 10 wherein the logic die further comprises:

a packet disassembler and data compare unit configured to receive data from a plurality of vaults, compare the received read data and couple results of the comparison to the tester over the third interface.

14. The memory device system of claim 13 wherein the read data from the plurality of vaults are coupled to the packet disassembler and data compare unit responsive to at least one read command and address coupled to the packet builder and broadcaster.

15. The memory device system of claim 10 further comprising a plurality of vault controllers, each coupled to a respective one of the plurality of vaults and configured to receive command and address signals from the switch and access their respective vault in accordance with the command and address signals.

16. The memory device system of claim 15 wherein the packet builder and broadcaster is configured to direct received command signals to a plurality of the vault controllers.

17. The memory device of claim 10 wherein the third interface is bi-directional and the plurality of link interfaces are bi-directional.

18. The memory device system of claim 10 wherein each of the memory device die comprise a respective dynamic random access memory device die.

19. A method of testing a plurality of stacked memory device die connected to each other and being connected to a logic circuit die on which the memory device die are stacked and being configured for access according to a plurality of vaults, the method comprising:

receiving at the logic circuit die a write command signal, an address signal and write data from separate interfaces;

combining, on the logic circuit die, the command and address signals and at least a portion of the write data into a packet;

broadcasting the packet to a plurality of the vaults;

writing the write data to a location corresponding to the address in each of the plurality of the vaults;

receiving at the logic circuit die a read command signal and an address signal from separate interfaces;

combining, on the logic circuit die, the command and address signals into a read packet;

broadcasting the read packet to the plurality of the vaults;

receiving read data responsive to the read packet from each of the plurality of the vertical vaults;

comparing the read data returned from each of the plurality of the vaults; and

outputting data to one of the separate interfaces corresponding to the comparison including an indication of whether any of the vaults returned read data different than any of the other plurality of vaults.

20. The method of testing according to claim 19 wherein each of the plurality of vaults comprise a plurality of memory devices interconnected in a vertical stack.

21. The method of testing according to claim 19 further comprising:

determining an error occurred in at least one of the plurality of vaults based on the output data; and

issuing a test command to fewer than all the plurality of vaults to determine the source of the error.

22. The method of testing according to claim 21 wherein the act of issuing the test command to fewer than all the plurality of vertical vaults comprises issuing the test command to a single vertical vault.

23. The method of testing according to claim 19 wherein the received read data from each of the plurality of vaults includes a packet and the act of comparing the read data includes disassembling each of the respective packets.

24. The method of testing according to claim 19 further comprising receiving wherein the output data is coupled to the interface from which the write data signal was received.

25. The method of testing according to claim 19 further comprising receiving a command signal placing the logic circuit die into a test mode.

26. The method of testing according to claim 19 further comprising coupling a conventional tester to the logic circuit die over the plurality of separate interfaces.