Selective Per-Cycle Masking Of Scan Chains For System Level Test

• US 20090300446A1
• Filed: 12/22/2008
• Published: 12/03/2009
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Mrugalski, Grzegorz, Czysz, Darjusz, Tyszer, Jerzy, Rajski, Janusz
• Granted Patent: US 8,166,359 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.

Claims

1. One or more computer readable media storing computer-executable instructions for causing a computer to perform any of the new and nonobvious methods or method acts described herein both alone and in combinations and subcombinations with one another.

2. A method of synthesizing compactors and/or X-masking circuitry comprising any of the new and nonobvious methods or method acts described herein both alone and in combinations and subcombinations with one another.

3. One or more computer-readable media storing design data for representing or implementing any of the new and nonobvious compactors and/or associated hardware described herein.

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