MODEL-BASED PROCESS SIMULATION SYSTEMS AND METHODS

• US 20090300573A1
• Filed: 05/29/2009
• Published: 12/03/2009
• Est. Priority Date: 06/03/2008
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Goossens, Ronaldus Johannes Gijsbertus, Ye, Jun, Cao, Yu, Shao, Wenjin, Koonmen, James Patrick
• Granted Patent: US 8,806,387 B2
• Time in Patent Office: Days
• US Class Current: 716/50
• CPC Class Codes: B29C 64/386 Data acquisition or data processing for additive manufacturing
• CPC Class Codes: G03F 7/70091 Illumination settings, i.e. intensity distribution in the pupil plane or angular distribution in the field plane; On-axis or off-axis settings, e.g. annular, dipole or quadrupole settings; Partial coherence control, i.e. sigma or numerical aperture [NA]
• CPC Class Codes: G03F 7/70458 Mix-and-match, i.e. multiple exposures of the same area using a similar type of exposure apparatus, e.g. multiple exposures using a UV apparatus
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70516 Calibration of components of the microlithographic apparatus, e.g. light sources, addressable masks or detectors
• CPC Class Codes: G03F 7/70525 Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.

Claims

1. A method for lithographic process simulation comprising:

maintaining a differential model that describes differences in imaging results attributable to differences in lithographic process parameters; and

generating simulated wafer contours using the the differential model.

2. The method of claim 1, wherein the differences in lithographic process parameters correspond to one or more of mask differences, resist differences, track differences, etch differences and scanner differences.

3. The method of claim 6, wherein the scanner differences include differences associated with one or more of optics, mechanics, control and device-specific laser drift.

4. The method of claim 1, wherein the simulated wafer contours correspond to wafer contours in resist.

5. The method of claim 1, wherein the simulated wafer contours correspond to wafer contours after etch.

6. The method of claim 1, wherein the simulated wafer contours include contours generated by lithographic processes mutually distinguishable by at least one different lithographic process parameter.

7. The method of claim 1, wherein the differential model characterizes differences in two lithographic process including two scanners.

8. The method of claim 1, wherein differences described by the differential model include tunable and non-tunable parameters.

9. The method of claim 7, further comprising deriving a model of one of the two scanners using the differential model and a model of the other scanner.

10. The method of claim 9, wherein the model of the other scanner is one of an OPC model and an OPC verification model.

11. A method for lithographic process simulation, comprising:

maintaining a sensitivity model that describes differences in imaging results attributable to differences in scanner settings for one scanner; and

generating simulated wafer contours using the sensitivity model.

12. The method of claim 11, wherein the simulated wafer contours correspond to wafer contours in resist.

13. The method of claim 11, wherein the simulated wafer contours correspond to wafer contours after etch.

14. The method of claim 11, wherein the simulated wafer contours include contours generated by lithographic processes mutually distinguishable by at least one different scanner setting parameter.

15. The method of claim 11, further comprising deriving a model of the scanner at a particular setting using the sensitivity model and a base model of the scanner at another setting.

16. The method of claim 15, wherein the base model of the scanner is one of an OPC model and an OPC verification model.

17. The method of claim 11 or 15, wherein the scanner settings relate to one or more of an illumination system, a projection system, a laser source and a wafer stage of the one scanner.

18. A method for calibrating a lithographic model, comprising:

performing a plurality of simulations of a lithographic process, wherein for each simulation, tunable settings of a process model are changed;

comparing simulated contours produced by the simulations with measured contours produced under corresponding changes in the lithographic process to identify differences between the simulated contours and the measured contours; and

calibrating parameters of the process model using a cost function based on the identified differences.

19. The method of claim 18, wherein the process model is a sensitivity model that describes differences in imaging results attributable to differences in apparatus settings for a lithographic apparatus.

20. A method for calibrating a lithographic model, comprising:

performing simulations of a lithographic process for a plurality of scanners, wherein a differential model characterizes scanner related differences in the lithographic process;

identifying differences between simulated contours produced by the simulations and corresponding measured contours obtained from the plurality of scanners under the simulated conditions; and

optimizing parameters of the differential model based on the identified differences.

21. The method of claim 20, wherein the step of optimizing includes adjusting tunable and non-tunable scanner parameters until differences in the simulated contours match corresponding differences in the measured contours.