Scheduling of Multiple Tasks in a System Including Multiple Computing Elements

• US 20090300629A1
• Filed: 06/02/2008
• Published: 12/03/2009
• Est. Priority Date: 06/02/2008
• Status: Abandoned Application

• Current Assignee: Mobileye Technologies Limited (Intel Corporation)
• Original Assignee: Mobileye Technologies Limited (Intel Corporation)
• Inventors: Rushinek, Elchanan, Pann, Arkady, Navon, Mois, Kreinin, Yossi, Sixou, Emmanuel
• Application Number:
  US12/131,173
• Publication Number:
  US 20090300629A1
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 2209/483 Multiproc
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

A method for controlling parallel process flow in a system including a central processing unit (CPU) attached to and accessing system memory, and multiple computing elements. The computing elements (CEs) each include a computational core, local memory and a local direct memory access (DMA) unit. The CPU stores in the system memory multiple task queues in a one-to-one correspondence with the computing elements. Each task queue, which includes multiple task descriptors, specifies a sequence of tasks for execution by the corresponding computing element. Upon programming the computing element with task queue information of the task queue, the task descriptors of the task queue in system memory are accessed. The task descriptors of the task queue are stored in the local memory of the computing element. The accessing and the storing of the data by the CEs is performed using the local DMA unit. When the tasks of the task queue are executed by the computing element, the execution is typically performed in parallel by at least two of the computing elements. The CPU is interrupted respectively by the computing elements only upon their fully executing the tasks of their respective task queues.

Claims

1. In a system including:

a central processing unit (CPU) operatively attached to and accessing a system memory; and

a plurality of computing elements, wherein the computing elements each include a computational core, local memory, and a local direct memory access (DMA) unit, wherein the local memory and the system memory are accessible by the computational core using the local DMA unit, a method comprising the steps of;

(a) storing by the CPU in the system memory a plurality of task queues in one-to-one correspondence with the computing elements, wherein each of said task queues includes a plurality of task descriptors which specify a sequence of tasks for execution by the computing elements;

(b) upon programming said computing element with task queue information of said task queue, accessing the task descriptors of said task queue in the system memory;

(c) storing said task descriptors of the task queue in local memory of the computing element;

wherein said accessing and said storing are performed using the local DMA unit of the computing element;

(d) executing the tasks of the task queue by the corresponding computing element, wherein said executing of the respective task queues is performed in parallel by at least two of said computing element; and

(e) interrupting respectively the CPU by the computing elements only upon fully executing all the tasks of the respective task queue.

2. The method, according to claim 1, further comprising the step of:

(f) storing results of said executing in the system memory in a plurality of address locations as indicated by said task queue information, wherein said storing of said results is performed by the local DMA unit of the computing element.

3. The method, according to claim 1, wherein the local memory of the computing element has insufficient capacity for storing simultaneously all the task descriptors of the task queue, wherein said accessing, said storing and said executing of said task queue are performed portion-by-portion, and upon generating results of said executing of a portion of said task queue, storing said results of said executing in a plurality of address locations of the local memory which previously stored the task descriptors already executed within said portion of said task queue.

4. The method, according to claim 1, wherein the task queue is part of a batch of task queues for execution by the computing element, said task queue information further including a pointer to the next task queue in the batch.

5. The method, according to claim 1, further comprising the steps of, prior to said accessing:

(f) providing each of the computing elements with a plurality of control registers;

(g) loading said control registers with said task queue information including;

(i) the number of tasks in the task queue, and (ii) a pointer in system memory to where said task descriptors reside.

6. The method, according to claim 5, wherein said task queue information further includes:

(iii) a results queue pointer which points to a location in the system memory for storing results of said executing.

7. A system comprising:

(a) a central processing unit (CPU);

(b) a system memory operatively attached to and accessed by said CPU; and

(c) a plurality of computing elements, wherein said computing elements each include a computational core, local memory, and a local direct memory access (DMA) unit, wherein said local memory and said system memory are accessible by said computational core using said local DMA units,

wherein said CPU stores in said system memory a plurality of task queues in one-to-one correspondence with said computing elements, wherein each task queue includes a plurality of task descriptors which specify a sequence of tasks for execution by said computing element,

wherein upon programming said computing element with task queue information of said task queue, said task descriptors of said task queue are accessed in system memory using said local DMA unit of said computing element,

wherein said task descriptors of said task queue are stored in local memory of said computing element using said local DMA unit of said computing element,

wherein said tasks of said task queue are executed by said computing element and at least two of said computing elements process respective task queues in parallel, and

wherein said CPU is interrupted by said computing elements only upon fully executing said tasks of said respective task queue.

8. The system, according to claim 7, further comprising:

(d) a plurality of control registers, wherein said control registers are loaded with said task queue information including;

(i) the number of tasks in the task queue; and

(ii) a pointer in system memory to where said task descriptors reside.

9. The system, according to claim 8, wherein said task queue information further includes:

(iii) a results queue pointer which points to a location in the system memory for storing results of said execution.

10. An image processing system for processing in real time multiple image frames, the system comprising:

(a) a central processing unit (CPU);

(b) a system memory operatively attached to and accessed by said CPU; and

(c) a plurality of computing elements, wherein said computing elements each include a computational core, local memory, and a local direct memory access (DMA) unit, wherein said local memory and said system memory are accessible by said computational core using said local DMA unit,

wherein said CPU stores in said system memory a plurality of task queues in one-to-one correspondence with said computing elements, wherein each task queue includes a plurality of task descriptors which specify a sequence of tasks for execution by said computing element,

wherein upon programming said computing element with task queue information of said task queue, said task descriptors of said task queue are accessed in system memory using said local DMA unit of said computing element,

wherein said task descriptors of said task queue are stored in local memory of said computing element using said local DMA unit of said computing element,

wherein said tasks of said task queue are executed by said computing element and at least two of said computational cores process respective task queues in parallel,

wherein said CPU is interrupted by said computing elements only upon fully executing said tasks of said respective task queue,

wherein at least one of the computing elements is programmed to classify an image portion of one of the image frames as an image of a known object, and

wherein another of the computing elements is programmed to track said image portion in real time from the previous image frame to the present. image frame.

11. The system, according to claim 10, wherein yet another of the computing elements is programmed for receiving the image frames and storing the image frames in real-time in the system memory.

12. The system, according to claim 10, wherein yet another of the computing elements is programmed for real-time reduced resolution image generation.

13. The system, according to claim 10, wherein yet another of the computing elements is programmed for real-time stereo processing of the multiple image frames simultaneously with another set of multiple image frames.

14. The system, according to claim 10, wherein yet another of the computing elements is programmed for real-time spatial filtration of at least a portion of one of the image frames.

15. The system, according to claim 10, wherein said computing elements are implemented as application specific integrated circuits (ASIC).