Methods for Wafer Scale Processing of Needle Array Devices
First Claim
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1. A method for wafer-scale fabrication of needle arrays comprising:
- (a) providing a wafer having an upper surface and a lower surface;
(b) mechanically modifying the upper surface to produce a plurality of vertically-extending columns;
(c) etching the wafer to produce a plurality of needles from the plurality of vertically-extending columns;
(d) coating tips of the plurality of needles with an electrically conductive coating;
(e) securing a carrier substrate to the lower surface of the wafer;
(d) separating the wafer into a plurality of individual needle arrays, each having at least one edge, while leaving the carrier substrate intact;
(g) encapsulating the individual needle arrays with an electrically insulative coating so that each edge is covered by the electrically insulative coating; and
(h) de-encapsulating the tips of the plurality of needles.
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Abstract
Methods of fabricating needle arrays on a wafer scale include etching a wafer of columns and needles and coating the same with an electrically insulating material and exposing electrically conductive tips. This process can benefit from using a slow spin speed to distribute resist material across the wafer before etching and using a carrier wafer to support singulated arrays to allow full coverage of upper array surfaces with electrically insulating materials. These processes allow for efficient high volume production of high count microelectrode arrays with a high repeatability and accuracy.
91 Citations
21 Claims
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1. A method for wafer-scale fabrication of needle arrays comprising:
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(a) providing a wafer having an upper surface and a lower surface; (b) mechanically modifying the upper surface to produce a plurality of vertically-extending columns; (c) etching the wafer to produce a plurality of needles from the plurality of vertically-extending columns; (d) coating tips of the plurality of needles with an electrically conductive coating; (e) securing a carrier substrate to the lower surface of the wafer; (d) separating the wafer into a plurality of individual needle arrays, each having at least one edge, while leaving the carrier substrate intact; (g) encapsulating the individual needle arrays with an electrically insulative coating so that each edge is covered by the electrically insulative coating; and (h) de-encapsulating the tips of the plurality of needles. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification