THIN FILM TRANSISTOR ARRAY PANEL

• US 20090302316A1
• Filed: 05/13/2009
• Published: 12/10/2009
• Est. Priority Date: 06/05/2008
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KIM, Ki-Won, YOUN, Jae-Hyoung, LEE, Young-Wook, LEE, Woo-Geun, KIM, Jong-In
• Granted Patent: US 8,604,469 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.

Claims

1. A thin film transistor array panel, comprising:

a substrate;

a gate line formed on the substrate and including a gate electrode;

a gate insulating layer formed on the gate line;

a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor;

a data line formed on the semiconductor and including a source electrode; and

a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor,

wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.

2. The thin film transistor array panel of claim 1, wherein the semiconductor is an oxide semiconductor.

3. The thin film transistor array panel of claim 2, wherein the oxide semiconductor comprises an oxide including zinc (Zn), gallium (Ga), tin (Sn) or indium (In), or a composite oxide thereof including zinc oxide (ZnO), indium-gallium-zinc oxide (InGaZnO4), indium-zinc oxide (In—

Zn—

O), or zinc-tin oxide (Zn—

Sn—

O).

4. The thin film transistor array panel of claim 3, further comprising:

a passivation layer formed on the data line and the drain electrode, and including a contact hole exposing the drain electrode; and

a pixel electrode formed on the passivation layer, and connected to the drain electrode through the contact hole.

5. The thin film transistor array panel of claim 4, wherein the passivation layer includes a lower inorganic layer and an upper organic layer, and the upper organic layer has a flat surface.

6. The thin film transistor array panel of claim 1, further comprising:

a passivation layer formed on the data line and the drain electrode, and including a contact hole exposing the drain electrode; and

a pixel electrode formed on the passivation layer, and connected to the drain electrode through the contact hole.

7. The thin film transistor array panel of claim 6, wherein the passivation layer includes a lower inorganic layer and an upper organic layer, and the upper organic layer has a flat surface.

8. A thin film transistor array panel, comprising:

a substrate;

a gate electrode formed on the substrate;

a gate insulating layer formed on the gate electrode; and

a semiconductor formed on the gate insulating layer,

wherein a channel of a thin film transistor comprises a portion of the semiconductor covering both side surfaces of the gate electrode and the upper surface of the gate electrode.

9. The thin film transistor array panel of claim 8, wherein the semiconductor is an oxide semiconductor.

10. The thin film transistor array panel of claim 9, wherein the oxide semiconductor comprises an oxide including zinc (Zn), gallium (Ga), tin (Sn) or indium (In), or a composite oxide thereof including zinc oxide (ZnO), indium-gallium-zinc oxide (InGaZnO4), indium-zinc oxide (In—

Zn—

O), or zinc-tin oxide (Zn—

Sn—

O).

11. A thin film transistor array panel, comprising:

a substrate;

a gate line formed on the substrate and including a gate electrode;

a gate insulating layer formed on the gate line;

a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor;

a data line formed on the semiconductor and including a source electrode; and

a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor,

wherein a width of the channel of the thin film transistor is increased by the width of both side surfaces of the gate electrode.

12. The thin film transistor array panel of claim 11, wherein the semiconductor is an oxide semiconductor.

13. The thin film transistor array panel of claim 12, wherein the oxide semiconductor comprises an oxide including zinc (Zn), gallium (Ga), tin (Sn) or indium (In), or a composite oxide thereof including zinc oxide (ZnO), indium-gallium-zinc oxide (InGaZnO4), indium-zinc oxide (In—

Zn—

O), or zinc-tin oxide (Zn—

Sn—

O).