SEMICONDUCTOR CIRCUIT HAVING CAPACITOR AND THIN FILM TRANSISTOR, FLAT PANEL DISPLAY INCLUDING THE SEMICONDUCTOR CIRCUIT, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR CIRCUIT

• US 20090302332A1
• Filed: 05/29/2009
• Published: 12/10/2009
• Est. Priority Date: 06/09/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Jun-woo, Yoon, Ju-Won, Kang, Chul-Kyu, Choi, Jong-Hyun, Kwon, Do-Hyun
• Granted Patent: US 8,704,235 B2
• Time in Patent Office: Days
• US Class Current: 257/88
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

A flat panel display including a semiconductor circuit, and a method of manufacturing the semiconductor circuit are disclosed. In one embodiment, the semiconductor circuit includes i) a substrate, ii) a semiconductor layer and a first capacitor electrode formed on the substrate, the first capacitor electrode being doped to be conductive, iii) an insulating layer covering the semiconductor layer and the first capacitor electrode, iv) a gate electrode disposed on the insulating layer and corresponding to a portion of the semiconductor layer, and v) a second capacitor electrode disposed on the insulating layer and corresponding to the first capacitor electrode, wherein the gate electrode is thicker than the second capacitor electrode.

Claims

1. A semiconductor circuit having a capacitor and a thin film transistor (TFT), the substrate comprising:

a substrate;

a semiconductor layer and a first capacitor electrode formed on the substrate, the first capacitor electrode being doped to be conductive;

an insulating layer covering the semiconductor layer and the first capacitor electrode;

a gate electrode disposed on the insulating layer and corresponding to a portion of the semiconductor layer; and

a second capacitor electrode disposed on the insulating layer and corresponding to the first capacitor electrode,

wherein the gate electrode is thicker than the second capacitor electrode.

2. The semiconductor circuit of claim 1, wherein a portion of the semiconductor layer that does not correspond to the gate electrode is doped with the same dopants as the first capacitor electrode.

3. The semiconductor circuit of claim 2, wherein a doping density of the portion of the semiconductor is heavier than a doping density of the first capacitor electrode.

4. The semiconductor circuit of claim 1, wherein the gate electrode comprises a first conductive layer corresponding to a portion of the semiconductor layer and a second conductive layer disposed on the first conductive layer.

5. The semiconductor circuit of claim 4, wherein the first conductive layer and the second capacitor electrode have substantially the same thickness.

6. The semiconductor circuit of claim 4, wherein a portion of the semiconductor layer that does not correspond to the gate electrode is doped with the same dopants as the first capacitor electrode.

7. The semiconductor circuit of claim 6, wherein a doping density of the portion of the semiconductor layer is heavier than a doping density of the first capacitor electrode.

8. The semiconductor circuit of claim 1, wherein the semiconductor layer and the first capacitor electrode have substantially the same thickness.

9. The semiconductor circuit of claim 1, wherein the gate electrode and second capacitor electrode are located at substantially the same distance from the substrate.

10. The semiconductor circuit of claim 1, wherein the gate electrode and second capacitor electrode are located directly above the semiconductor layer and the first capacitor electrode, respectively.

11. A flat panel display, comprising:

a semiconductor circuit comprising i) a semiconductor layer and a first capacitor electrode formed on the same layer, the first capacitor electrode being doped to be conductive, ii) an insulating layer covering the semiconductor layer and the first capacitor electrode, iii) a gate electrode disposed on the insulating layer and corresponding to the first capacitor electrode, and iv) a second capacitor electrode disposed on the insulating layer and corresponding to the first capacitor electrode, wherein the gate electrode is thicker than the second capacitor electrode;

source and drain electrodes contacting the semiconductor layer; and

a light emitting device electrically connected to at least one of the source and drain electrodes.

12. The flat panel display of claim 11, wherein the gate electrode comprises a first conductive layer corresponding to a portion of the semiconductor layer and a second conductive layer disposed on the first conductive layer.

13. A method of manufacturing a semiconductor circuit having a capacitor and a thin film transistor (TFT), the method comprising:

providing a substrate;

forming a first semiconductor layer and a second semiconductor layer on the substrate, wherein the first semiconductor layer is configured to be formed as the TFT, and wherein the second semiconductor layer is configured to be formed as a first capacitor electrode;

forming an insulating layer to cover the first and second semiconductor layers;

forming a gate electrode corresponding to a portion of the first semiconductor layer on the insulating layer;

forming a second capacitor electrode corresponding to the second semiconductor layer on the insulating layer, wherein the gate electrode is thicker than the second capacitor electrode; and

through the insulating layer, doping the second semiconductor layer so that the second semiconductor layer becomes conductive.

14. The method of claim 13, wherein the gate electrode and the second capacitor electrode are substantially simultaneously formed via a half-tone mask.

15. The method of claim 13, wherein forming the gate electrode comprises:

forming a first conductive layer corresponding to the portion of the first semiconductor layer on the insulating layer; and

forming a second conductive layer on the first conductive layer.

16. The method of claim 15, wherein the first conductive layer and the second capacitor electrode are substantially simultaneously formed and have substantially the same thickness.

17. The method of claim 13, wherein the doping comprises substantially simultaneously doping i) the second semiconductor layer, and ii) a portion the first semiconductor layer that does not correspond to the gate electrode.

18. The method of claim 17, wherein a doping density of the portion of the first semiconductor layer is heavier than a doping density of the second semiconductor layer.

19. The method of claim 13, wherein the gate electrode and second capacitor electrode are located at substantially the same distance from the substrate.

20. The method of claim 13, wherein the gate electrode and second capacitor electrode are located directly above the semiconductor layer and the first capacitor electrode, respectively.