Structure and Method for Forming Power Devices with Carbon-containing Region

• US 20090302381A1
• Filed: 12/12/2008
• Published: 12/10/2009
• Est. Priority Date: 12/14/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Pan, James
• Granted Patent: US 7,994,573 B2
• Time in Patent Office: Days
• US Class Current: 257/332
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. The body regions form p-n junctions with the semiconductor region. Source regions of the second conductivity type extend over the body regions. The source regions form p-n junctions with the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric. A carbon-containing region extends in the semiconductor region below the body regions.

Claims

1. A field effect transistor (FET), comprising:

body regions of a first conductivity type over a semiconductor region of a second conductivity type, the body regions forming p-n junctions with the semiconductor region;

source regions of the second conductivity type over the body regions, the source regions forming p-n junctions with the body regions;

gate electrodes extending adjacent to but being insulated from the body regions by a gate dielectric;

a carbon-containing region extending in the semiconductor region below the body regions.

2. The FET of claim 1 wherein the semiconductor region further comprises:

a substrate over which the carbon-containing region extends; and

a drift region of the second conductivity type extending between the carbon-containing region and the body regions, wherein the substrate has a doping concentration greater than that of the drift region.

3. The FET of claim 2 wherein the carbon-containing region is in direct contact with the substrate and is spaced from the body regions.

4. The FET of claim 1, wherein each gate electrode is disposed in a trench extending adjacent the body regions and terminating within the semiconductor region.

5. The FET of claim 4, wherein each trench further includes a shield electrode disposed below the gate electrode, the gate and shield electrodes being insulated from one another by an inter-electrode dielectric layer.

6. The FET of claim 4 wherein each trench includes a thick bottom dielectric extending along the bottom of the trench below the gate electrode.

7. The FET of claim 1, wherein the gate electrodes extend laterally over the semiconductor and body regions and overlap the source regions.

8. The FET of claim 4, wherein the entirety of carbon-containing region extends below the trenches.

9. The FET of claim 4, wherein the carbon-containing region abuts sidewalls of the trenches.

10. The FET of claim 1, wherein the carbon-containing region is of the second conductivity type.

11. A method of forming a field effect transistor (FET), comprising:

forming a carbon-containing region over a substrate;

forming an epitaxial layer over the carbon-containing region, the epitaxial layer having a lower doping concentration than the substrate;

forming a body region of a first conductivity type in the epitaxial layer, the epitaxial layer being of a second conductivity type, the body region forming a p-n junction with the epitaxial layer;

forming gate electrodes adjacent to but insulated from the body regions; and

forming source regions of the second conductivity type in the body regions, the source regions forming p-n junctions with the body regions.

12. The method of claim 11 wherein the carbon-containing region is formed epitaxially.

13. The method of claim 11 wherein the carbon-containing region is in direct contact with the substrate.

14. The method of claim 11, wherein the carbon-containing region is of the second conductivity type.

15. The method of claim 11 wherein the carbon in the carbon-containing region has a Gaussian profile.

16. The method of claim 11, further comprising:

forming trenches extending into semiconductor regions, the trenches housing the gate electrodes.

17. The method of claim 16 further comprising:

before forming the gate electrodes;

forming a shield dielectric layer lining lower sidewalls and bottom of each trench;

forming a shield electrode in a lower portion of each trench; and

forming an inter-electrode dielectric layer in each trench over the shield electrode.

18. The method of claim 16 further comprising:

before forming the gate electrode, forming a thick bottom dielectric extending along the bottom of the trench.

19. The method of claim 11, wherein the gate electrodes extend laterally over the semiconductor and body regions and overlap the source regions.

20. The method of claim 16 wherein the entirety of carbon-containing region extends below the trenches.

21. The FET of claim 16, wherein the trenches extend into the carbon-containing region.