INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF

• US 20090302387A1
• Filed: 08/14/2009
• Published: 12/10/2009
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: HSU, LOUIS C., JOSHI, RAJIV V., GLUSCHENKOV, OLEG
• Granted Patent: US 7,968,944 B2
• Time in Patent Office: Days
• US Class Current: 257/350
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

Claims

1. An Integrated Circuit (IC) chip comprising:

a plurality of logic circuits formed on a surface of a silicon chip;

ones of said plurality of logic circuits including a plurality of bulk Field Effect Transistors (FETs); and

at least one other of said plurality of logic circuits including a plurality of Silicon-on-Insulator (SOI) FETs.

2. An IC chip as in claim 1, further comprising guardrings isolating regions of said bulk FETs from regions of said SOI FETs.

3. An IC chip as in claim 2, wherein said plurality of SOI FETs comprises:

a plurality of Partially Depleted SOI (PD-SOI) FETs; and

a plurality of Fully Depleted SOI (FD-SOI) FETs, guardrings further isolating regions of said PD-SOI FETs from regions of said FD-SOI FETs.

4. An IC chip as in claim 3, wherein said insulator is buried oxide (BOX) and said regions of said PD-SOI FETs are seamlessly horizontally located adjacent to said regions of said FD-SOI FETs separated by one or more said guardrings.

5. An IC chip as in claim 2, wherein said guardrings are isolation trenches.

6. An IC chip as in claim 5, wherein said plurality isolation trenches are shallow trench isolation trenches (STI).

7. An IC chip as in claim 6, wherein said surface of said chip is substantially planar.

8. An IC chip as in claim 1, wherein said surface of said chip is substantially planar.

9. A bulk CMOS Integrated Circuit (IC) chip comprising:

a plurality of logic circuits formed on a surface of a silicon chip;

ones of said plurality of logic circuits including a plurality of bulk Field Effect Transistors (FETs);

a plurality of chip areas with pockets of buried insulator strata; and

other ones of said plurality of logic circuits being Silicon-on-Insulator (SOI) FET circuits located in said plurality of chip areas.

10. A bulk CMOS IC chip as in claim 9, further comprising guardrings isolating regions of said bulk FETs from regions of said SOI FETs.

11. A bulk CMOS IC chip as in claim 10, wherein said pockets of insulator strata are located at a plurality of depths beneath said surface, each SOI FET being above one of said insulator strata, guardrings further isolating areas of each depth from other said areas of different said depths.

12. A bulk CMOS IC chip as in claim 11, wherein said plurality of depths is two and said plurality of SOI FET circuits comprise:

at least one Partially Depleted SOI (PD-SOI) FET circuit located above an insulator stratum at a first depth; and

at least one Fully Depleted SOI (FD-SOI) FET circuit located above an insulator stratum at a second depth.

13. A bulk CMOS IC chip as in claim 12, wherein said insulator strata material is buried oxide (BOX) and said regions of said PD-SOI FETs are seamlessly horizontally located adjacent to said regions of said FD-SOI FETs separated by one or more said guardrings.

14. A bulk CMOS IC chip as in claim 10, wherein said guardrings are isolation trenches to said insulator strata.

15. A bulk CMOS IC chip as in claim 14, wherein said plurality isolation trenches are shallow trench isolation trenches (STI).

16. A bulk CMOS IC chip as in claim 15, wherein said surface of said chip is substantially planar.