CMOS INTEGRATED CIRCUITS WITH BONDED LAYERS CONTAINING FUNCTIONAL ELECTRONIC DEVICES

• US 20090302394A1
• Filed: 09/24/2008
• Published: 12/10/2009
• Est. Priority Date: 06/10/2008
• Status: Active Grant

• Current Assignee: Toshiba America Research Inc (Toshiba Corporation)
• Original Assignee: Toshiba America Research Inc (Toshiba Corporation)
• Inventors: Fujita, Shinobu
• Granted Patent: US 8,716,805 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Abstract

A complementary metal oxide semiconductor (CMOS) circuit having integrated functional devices such as nanowires, carbon nanotubes, magnetic memory cells, phase change memory cells, ferroelectric memory cells or the like. The functional devices are integrated with the CMOS circuit. The functional devices are bonded (e.g. by direct bonding, anodic bonding, or diffusion bonding) to a top surface of the CMOS circuit. The functional devices are fabricated and processed on a carrier wafer, and an attachment layer (e.g. SiO2) is deposited over the functional devices. Then, the CMOS circuit and attachment layer are bonded. The carrier wafer is removed (e.g. by etching). The functional devices remain attached to the CMOS circuit via the attachment layer. Apertures are etched through the attachment layer to provide a path for electrical connections between the CMOS circuit and the functional devices.

Claims

1. A complementary metal oxide semiconductor (CMOS) circuit with integrated functional devices, comprising:

a) a substrate having CMOS devices;

b) a wiring layer disposed on the CMOS devices, wherein the wiring layer includes electrically conductive wiring and a dielectric layer;

c) a first attachment layer bonded to the dielectric layer;

d) a first functional device disposed on the attachment layer;

e) an electrical connection between the electrically conductive wiring and the functional device.

2. The CMOS circuit of claim 1, wherein the attachment layer and the dielectric layer are made of substantially the same material.

3. The CMOS circuit of claim 1, wherein the attachment layer has an aperture, and the electrical connection extends through the aperture.

4. The CMOS circuit of claim 1, further comprising a second attachment layer disposed on the first attachment layer, and a second functional device disposed on the second attachment layer.

5. The CMOS circuit of claim 1, wherein the functional device includes a carbon nanotube or nanowire.

6. The CMOS circuit of claim 1, wherein the functional device includes a carbon nanotube transistor or nanowire transistor.

7. The CMOS circuit of claim 1, wherein the functional device is a magnetic memory device, a phase change memory device, a ferroelectric memory device, or a resistive memory device.

8. A method for fabricating a CMOS circuit with integrated functional devices, comprising the steps of:

a) fabricating a CMOS circuit with a dielectric layer and terminals in the dielectric layer;

b) fabricating a functional device on a carrier substrate;

c) depositing an attachment layer over the functional device;

d) bonding the dielectric layer and attachment layer so that the CMOS circuit and carrier substrate are attached;

e) releasing or removing the carrier substrate;

f) fabricating electrical connections between the functional device and the terminals.

9. The method of claim 8, wherein the attachment layer and an uppermost sublayer of the dielectric layer are made of substantially the same material.

10. The method of claim 8, wherein the attachment layer and an uppermost sublayer of the dielectric layer are made of SiO2 or glass.

11. The method of claim 8, wherein step (d) is performed by application of heat and pressure.

12. The method of claim 8, wherein the CMOS circuit is heated to temperatures less than 400 C in step (d).

13. The method of claim 8, wherein the carrier substrate is removed by etching the carrier substrate.

14. The method of claim 8, wherein the carrier substrate is released by etching or fracturing a spacer layer between the carrier substrate and the functional device.

15. A complementary metal oxide semiconductor (CMOS) circuit, comprising:

a) a substrate having CMOS devices;

b) a wiring layer disposed on the CMOS devices, wherein the wiring layer includes electrically conductive wiring and a dielectric layer;

c) a first attachment layer bonded to the dielectric layer;

d) an aperture in the attachment layer;

e) a first functional device disposed on the attachment layer;

f) an electrical connection between the electrically conductive wiring and the functional device, and extending through the aperture.

16. The CMOS circuit of claim 15, wherein the attachment layer and the dielectric layer are made of substantially the same material.

17. The CMOS circuit of claim 15, further comprising a second attachment layer disposed on the first attachment layer, and a second functional device disposed on the second attachment layer.

18. The CMOS circuit of claim 15, wherein the functional device includes a carbon nanotube transistor or nanowire transistor.

19. The CMOS circuit of claim 15, wherein the functional device is a magnetic memory device, a phase change memory device, a ferroelectric memory device, or a resistive memory device.