METHOD FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES

• US 20090302405A1
• Filed: 08/12/2009
• Published: 12/10/2009
• Est. Priority Date: 07/29/2005
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Dalton, Timothy J., Wong, Keith Kwong Hon, Yang, Chih-Chao, Clevenger, Lawrence A., Radens, Carl, Gaidis, Michael C., Hsu, Louis L. C.
• Granted Patent: US 7,825,420 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

Claims

1. A magnetic random access memory (MRAM) device, comprising:

a magnetic tunnel junction (MTJ) stack formed over a lower wiring level;

a hardmask formed on said MTJ stack;

an upper wiring level formed over said hardmask, said upper wiring level comprising a slot via bitline formed therein, said slot via bitline in contact with said hardmask and in contact with an etch stop layer at least partially surrounding sidewalls of said hardmask, wherein said etch stop layer comprises a material that is selectively etched with respect to said hardmask layer;

a conductive lateral strap upon which said MTJ stack is formed;

a strap via connecting said strap to a first conductor within said lower wiring level;

a logic via formed on a second conductor within said lower level in a peripheral portion of the device; and

an upper level logic wiring conductor in contact with said logic via.

2. A method for forming a magnetic random access memory (MRAM) device, the method comprising:

forming a magnetic tunnel junction (MTJ) stack over a lower wiring level;

forming a hardmask on said MTJ stack; and

forming an upper wiring level over said hardmask, said upper wiring level comprising a slot via bitline formed therein, said slot via bitline in contact with said hardmask and in contact with an etch stop layer at least partially surrounding sidewalls of said hardmask.

3. The method of claim 2, further comprising forming said MTJ stack upon a conductive lateral strap, said strap connected to a first conductor within said lower wiring level through a strap via.

4. The method of claim 3, further depositing said etch stop layer over a first dielectric layer, said strap, said MTJ stack, and said hardmask.

5. The method of claim 4, further comprising forming a second dielectric layer over said etch stop layer, and exposing a portion of said etch stop layer directly over said hardmask layer, wherein said etch stop layer is selectively etched with respect to said second dielectric layer.

6. The method of claim 5, wherein said portion of said etch stop layer is exposed by chemical mechanical polishing of said second dielectric layer.

7. The method of claim 5, further comprising selectively etching said etch stop layer with respect to said hardmask layer so as to expose said hardmask.

8. The method of claim 5, further comprising removing said second dielectric and said etch stop layer atop said hardmask by chemical mechanical polishing, such that the top of said hardmask is exposed without further selective etch.

9. The method of claim 7, further comprising:

forming a third dielectric layer over said second dielectric layer and said exposed hardmask; and

implementing a first patterning and etching step to define said slot via bitline in said third and said second dielectric layers.

10. The method of claim 9, wherein said first patterning and etching step is also used to pattern a logic via in a peripheral section of the MRAM device.

11. The method of claim 10, further comprising implementing a second patterning and etching step to define an upper level wiring trench above said logic via, wherein said logic via is further etched through said etch stop layer and said first dielectric layer so as to land on said lower wiring level, and wherein said slot via bitline is masked so as to prevent etching of said slot via bitline through said etch stop layer.

12. The method of claim 9, wherein said logic via is further etched through said etch stop layer so as to land on a conductive landing pad formed at the same level as said strap via, wherein said slot via bitline is masked so as to prevent etching through said etch stop layer.

13. The method of claim 12, further comprising filling said slot via bitline, said logic via and said upper level logic wiring trench with conductive metal, and polishing to planarize and isolate in Damascene fashion.

14. A method for forming a magnetic random access memory (MRAM) device, the method comprising:

forming, in an array portion of the device, a strap via over a first conductor in a lower wiring level, and forming, in a peripheral portion of the device, a conductive landing area over a second conductor in said lower wiring level;

forming a metal strap over said strap via;

forming a patterned magnetic tunnel junction (MTJ) stack over said metal strap, said MTJ stack having a patterned hardmask formed thereupon;

forming an etch stop layer upon said conductive landing area, said strap layer, and said hardmask;

forming a first dielectric layer on said etch stop layer, exposing a first portion of said etch stop layer, and selectively etching said first portion of said etch stop layer so as to expose said hardmask;

forming a second dielectric layer upon said first dielectric layer and said hardmask;

patterning and etching a slot via bitline opening over said hardmask, and patterning and etching a logic via opening over said conductive landing area, said slot via bitline opening and said logic via opening formed within said first and second dielectric layers;

extending said logic via opening to etch through a second portion of said etch stop layer so as to expose said conductive landing area;

patterning an upper level logic wiring trench over said logic via while masking said slot via bitline opening; and

filling said slot via bitline, said logic via and said upper level logic wiring trench with conductive metal.