Micro-Electromechanical System Devices

• US 20090302415A1
• Filed: 06/04/2008
• Published: 12/10/2009
• Est. Priority Date: 06/04/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Gruenberger, Robert, Winkler, Bernhard, Mueller, Karl-Heinz
• Granted Patent: US 8,125,046 B2
• Time in Patent Office: Days
• US Class Current: 257/508
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit

Abstract

Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.

Claims

1. A micro-electromechanical system (MEMS) device, comprising:

a semiconductive layer disposed over a substrate;

a trench disposed in the semiconductive layer, the trench comprising a first sidewall and an opposite second sidewall;

a first insulating material layer disposed over an upper portion of the first sidewall;

a conductive material disposed within the trench; and

a first air gap disposed between the conductive material and the semiconductive layer.

2. The MEMS device of claim 1, wherein the semiconductive layer comprises a resonator layer, wherein the resonator layer comprises upper, middle and lower layers, the upper layer disposed on the middle layer, the middle layer disposed on the lower layer, wherein the upper and lower layers comprise a lower conductivity than the middle layer.

3. The MEMS device of claim 1, wherein the first air gap is disposed on the second sidewall and a lower portion of the first sidewall.

4. The MEMS device of claim 1, wherein a second air gap is disposed between at least a portion of the substrate and at least a portion of the semiconductive layer, the first and second air gaps being connected.

5. The MEMS device of claim 4, wherein a third air gap extends over a top surface of the semiconductive layer, the third air gap being connected to the first air gap.

6. The MEMS device of claim 5, wherein the third air gap is encapsulated by a second insulating layer.

7. The MEMS device of claim 1, wherein the first air gap is further disposed between the conductive material and the substrate.

8. The MEMS device of claim 1, further comprising a third insulating layer, the third insulating layer disposed adjacent the first air gap and between the substrate and the semiconductive layer.

9. The MEMS device of claim 1, wherein the semiconductive layer comprises a first layer, the first layer being capacitively coupled to the conductive material through the first air gap.

10. The MEMS device of claim 9, wherein the semiconductive layer comprises second and third layers, the second layer disposed above the first layer and the third layer disposed below the first layer, the second and third layers comprising a higher resistance than the first layer.

11. The MEMS device of claim 1, wherein the semiconductive layer comprises an oscillating element, and wherein the oscillating element comprises a resonator, an actuator, a sensor, a switch, or an accelerometer.

12. The MEMS device of claim 1, wherein the first air gap comprises a thickness of about 500 nm or less to about 5 nm.

13. The MEMS device of claim 1, wherein the trench comprises a depth from about 500 nm to about 10000 nm, and wherein the trench comprises a ratio of depth to width that is less than about 10:

1, and wherein the semiconductive layer comprises a thickness of about 250 nm to about 10000 nm.

14. The MEMS device of claim 1, further comprising:

an additional trench disposed in the semiconductor layer, the conductive material disposed within the additional trench, the additional trench comprising a third sidewall and an opposite fourth sidewall;

a fourth insulating material layer disposed over an upper portion of the third sidewall; and

a fifth air gap disposed between the fourth sidewall and the semiconductive layer.

15. A semiconductor chip comprising:

a semiconductive layer disposed over a substrate;

a first trench disposed in the semiconductive layer, the first trench comprising a first sidewall and an opposite second sidewall;

a first layer comprising an insulating material disposed over an upper portion of the first sidewall;

a conductive material disposed in the first trench;

a first air gap disposed between the conductive material and the semiconductive layer, the first air gap, the conductive material, and the semiconductive layer comprising a MEMS device; and

bipolar and CMOS transistors disposed in the semiconductor layer, the bipolar and CMOS transistors separated from the MEMS device by a second trench, the second trench filled with the insulating material.

16. The semiconductor chip of claim 15, further comprising a trench capacitor, the trench capacitor comprising:

a third trench disposed in the semiconductor layer, the third trench lined with the first layer comprising the insulating material, wherein the third trench is filled with the conductive material.

17. A semiconductor chip comprising:

a first electrode of a deep trench capacitor comprising a conductive material disposed in a first trench;

a capacitive dielectric of the deep trench capacitor comprising an insulating liner disposed between the conductive material and a semiconductor layer;

a second electrode of the deep trench capacitor comprising the semiconductor layer;

a driver electrode of a MEMS device comprising the conductive material disposed in a second trench, the first and second trenches disposed in the semiconductor layer;

an air gap disposed between the driver electrode and the semiconductor layer; and

a collector region of a bipolar device and a resonator electrode of the MEMS device comprising a highly doped region disposed in the semiconductor layer.

18. The semiconductor chip of claim 17, further comprising:

another deep trench, the another deep trench separating a first part of the semiconductor layer comprising the resonator electrode of the MEMS device with a second part of the semiconductor layer comprising the collector region of the bipolar device; and

a capacitor dielectric comprising the insulating liner, the insulating liner filling the another deep trench, the capacitor dielectric and the first and second parts of the semiconductor layer forming a capacitor.

19. A method of manufacturing a semiconductor chip comprising MEMS devices, the method comprising:

forming a semiconductive layer over a substrate, the substrate comprising a buried oxide layer;

forming a first trench in the semiconductive layer, the first trench exposing the buried oxide layer;

forming an insulating material layer over a first sidewall and an opposite second sidewall of the first trench and exposed buried oxide layer;

filling the first trench with a conductive material; and

forming an air gap by removing the insulating material layer from the second sidewall, the air gap being formed around top and bottom surfaces of the semiconductive layer.

20. The method of claim 19, wherein forming the semiconductive layer comprises:

selectively depositing a first semiconductive layer;

selectively doping the first semiconductive layer to form a first highly doped region;

selectively depositing a second semiconductive layer; and

selectively doping the second semiconductive layer to form a second highly doped region, wherein the second highly doped region is disposed above the first highly doped region.

21. The method of claim 20, wherein the first highly doped region comprises resonator electrode regions of the MEMS devices.

22. The method of claim 21, wherein the first highly doped region comprises collector regions of bipolar transistors.

23. The method of claim 20, wherein the second highly doped region comprises contacts and/or collector regions of bipolar transistors.

24. The method of claim 20, further comprising:

forming base and emitter regions of bipolar transistors on the second semiconductive layer.

25. The method of claim 20, further comprising:

forming source/drain regions, source/drain extension regions, and channel regions of CMOS transistors on the second semiconductive layer.

26. The method of claim 19, further comprising:

forming an isolation trench by forming a second trench in the semiconductive layer, the first trench and the second trench formed using a common etch process, the second trench being narrower than the first trench, wherein forming an insulating material fills up the second trench.

27. The method of claim 19, further comprising:

forming a trench capacitor by forming a third trench in the semiconductive layer, the first trench and the third trench formed using a common etch process, the third trench being about identical to the first trench.

28. A method of manufacturing a semiconductor chip comprising a MEMS device, the method comprising:

epitaxially growing a lightly doped first semiconductive layer over a substrate, the substrate comprising a buried oxide layer;

doping the first semiconductive layer to form a first highly doped region;

epitaxially growing a lightly doped second semiconductive layer on the first semiconductive layer;

forming first and second trenches in the first and second semiconductive layers, the first and second trenches exposing the buried oxide layer;

forming an insulating layer over the first and second trenches, wherein the insulating layer fills the second trench;

filling the first trench with a conductive material; and

forming an air gap in the first trench by removing the insulating layer, the air gap being formed on a top surface of the second semiconductive layer and a top surface of the substrate.