WIRING SUBSTRATE, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF

• US 20090302457A1
• Filed: 05/14/2009
• Published: 12/10/2009
• Est. Priority Date: 06/10/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: AOKI, Tomoyuki, CHIDA, Akihiro
• Granted Patent: US 8,044,499 B2
• Time in Patent Office: Days
• US Class Current: 257/702
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2224/29499 Shape or distribution of the fillers
• CPC Class Codes: H01L 23/3733 having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures H01L23/3732, H01L23/3737 take precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01067 Holmium [Ho]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0366 reinforced, e.g. by fibres, fabrics H05K1/036 takes precedence
• CPC Class Codes: H05K 2201/029 Woven fibrous reinforcement or textile textile substrates H05K1/038
• CPC Class Codes: H05K 2203/1147 Sealing or impregnating, e.g. of pores
• CPC Class Codes: H05K 3/4069 for via connections in organic insulating substrates
• CPC Class Codes: H05K 3/4647 : by applying an insulating layer around previously made via studs
• CPC Class Codes: Y10T 442/2418 : Coating or impregnation increases electrical conductivity or anti-static quality

Abstract

A wiring substrate is provided, including an insulating resin layer which is provided on both surfaces of a sheet-like fibrous body and with which the sheet-like fibrous body is impregnated, and a through wiring provided in a region surrounded by the insulating resin layer. The through wiring is formed using a conductive material, the conductive material is exposed on both surfaces of the insulating resin layer, the sheet-like fibrous body is positioned in the conductive material, and the sheet-like fibrous body is impregnated with the conductive material. A manufacturing method of the wiring substrate is also provided.

Claims

1. A wiring substrate comprising:

an insulating resin layer provided on both surfaces of a sheet-like fibrous body, the sheet-like fibrous body impregnated with the insulating resin layer; and

a wiring surrounded by the insulating resin layer, the wiring comprising a conductive material, the wiring penetrating the sheet-like fibrous body,

wherein a portion of the sheet-like fibrous body is positioned in the wiring,

wherein the wiring is exposed on both surfaces of the insulating resin layer, and

wherein the sheet-like fibrous body is impregnated with the conductive material.

2. A manufacturing method of a wiring substrate, comprising the steps of:

impregnating a first region of a sheet-like fibrous body with a conductive resin, whereby forming a wiring, the wiring penetrating the sheet-like fibrous body; and

impregnating a second region of the sheet-like fibrous body with an insulating resin layer, the second region surrounding the first region,

wherein a portion of the sheet-like fibrous body is positioned in the wiring, and

wherein the wiring is exposed on both surfaces of the insulating resin layer.

3. A semiconductor device comprising:

a resin-impregnated fibrous-body composite substrate including

an insulating resin layer provided on both surfaces of a sheet-like fibrous body, the sheet-like fibrous body impregnated with the insulating resin layer; and

a first wiring surrounded by the insulating resin layer, the first wiring comprising a conductive material, the first wiring penetrating the sheet-like fibrous body,

wherein a portion of the sheet-like fibrous body is positioned in the first wiring,

wherein the first wiring is exposed on both surfaces of the insulating resin layer, and

wherein the sheet-like fibrous body is impregnated with the conductive material; and

an integrated circuit chip including

a thin film transistor;

an insulating layer over the thin film transistor; and

a second wiring on the insulating layer,

wherein the integrated circuit chip is in close contact with the resin-impregnated fibrous-body composite substrate so that the second wiring is in contact with the first wiring.

4. A manufacturing method of a semiconductor device comprising the steps of:

forming a thin film transistor;

forming an insulating layer over the thin film transistor;

forming a second wiring on the insulating layer;

impregnating a first region of a sheet-like fibrous body with a conductive resin, whereby forming a first wiring, the first wiring being in contact with the second wiring, the first wiring penetrating the sheet-like fibrous body; and

impregnating a second region of the sheet-like fibrous body with an insulating resin layer, the second region surrounding the first region,

wherein a portion of the sheet-like fibrous body is positioned in the first wiring, and

wherein the first wiring is exposed on both surfaces of the insulating resin layer.