Prepreg, Method for Manufacturing Prepreg, Substrate, and Semiconductor Device

• US 20090302462A1
• Filed: 11/30/2006
• Published: 12/10/2009
• Est. Priority Date: 12/01/2005
• Status: Active Grant

• Current Assignee: Sumitomo Bakelite Company Limited
• Original Assignee: Sumitomo Bakelite Company Limited
• Inventors: Baba, Takayuki, Hosomi, Takeshi, Yuasa, Maroshi, Hamaya, Kazuya
• Granted Patent: US 8,044,505 B2
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: B32B 2260/021 Fibrous or filamentary layer
• CPC Class Codes: B32B 2260/046 Synthetic resin
• CPC Class Codes: B32B 2262/02 Synthetic macromolecular fibres
• CPC Class Codes: B32B 2262/0253 Polyolefin fibres
• CPC Class Codes: B32B 2262/0261 Polyamide fibres
• CPC Class Codes: B32B 2262/0269 Aromatic polyamide fibres
• CPC Class Codes: B32B 2262/0276 Polyester fibres
• CPC Class Codes: B32B 2262/101 Glass fibres
• CPC Class Codes: B32B 2264/102 Oxide or hydroxide
• CPC Class Codes: B32B 2307/202 Conductive
• CPC Class Codes: B32B 2457/00 Electrical equipment
• CPC Class Codes: B32B 2457/14 Semiconductor wafers
• CPC Class Codes: B32B 27/08 of synthetic resin
• CPC Class Codes: B32B 27/20 using fillers, pigments, thixotroping agents
• CPC Class Codes: B32B 27/281 comprising polyimides
• CPC Class Codes: B32B 27/36 comprising polyesters
• CPC Class Codes: B32B 29/005 next to another layer of paper or cardboard layer
• CPC Class Codes: B32B 5/022 Non-woven fabric
• CPC Class Codes: B32B 5/024 Woven fabric
• CPC Class Codes: B32B 5/145 Variation across the thickness of the layer
• CPC Class Codes: B32B 5/26 : another layer next to it also being fibrous or filamentary relative arrangement of fibres or filaments of different layers B32B5/12
• CPC Class Codes: C08J 5/244 : using glass fibres
• CPC Class Codes: C08J 5/249 : characterised by the additives used in the prepolymer mixture
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8121 : using a reflow oven
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/145 : Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H05K 1/0366 : reinforced, e.g. by fibres, fabrics H05K1/036 takes precedence
• CPC Class Codes: H05K 2201/0191 : wherein the thickness of the dielectric plays an important role
• CPC Class Codes: H05K 2201/0195 : Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 3/4626 : characterised by the insulating layers or materials H05K3/4688 takes precedence
• CPC Class Codes: Y10T 156/10 : Methods of surface bonding and/or assembly therefor
• CPC Class Codes: Y10T 428/2495 : Thickness [relative or absolute]

Abstract

A prepreg which can meet a demand for thickness reduction is provided. The prepreg has first and second resin layers having different applications, functions, capabilities, or properties, and allows an amount of a resin composition in each of the first and second resin layers to be set appropriately depending on a circuit wiring portion to be embedded into the second resin layer. Further, a method for manufacturing the above prepreg, and a substrate and a semiconductor device having the prepreg are also provided. The prepreg according to the present invention includes a core layer including a sheet-shaped base member and having one surface and the other surface which is opposite to the one surface, the first resin layer provided on the one surface of the core layer and formed of a first resin composition, and the second resin layer provided on the other surface of the core layer and formed of a second resin composition, wherein at least one of a requirement that a thickness of the first resin layer is different from that of the second resin layer and a requirement that a constitution of the first resin composition is different from that of the second resin composition is satisfied.

Claims

1. A prepreg, comprising:

a core layer including a sheet-shaped base member, the core layer having one surface and the other surface which is opposite to the one surface;

a first resin layer provided on the one surface of the core layer, the first resin layer formed of a first resin composition; and

a second resin layer provided on the other surface of the core layer, the second resin layer formed of a second resin composition,

wherein at least one of a requirement that a thickness of the first resin layer is different from that of the second resin layer and a requirement that a constitution of the first resin composition is different from that of the second resin composition is satisfied.

2. The prepreg as claimed in claim 1, wherein the constitution of the first resin composition is different from that of the second resin composition, and

wherein the prepreg is adapted to be used in a state that a conductor layer is provided on the first resin layer.

3. The prepreg as claimed in claim 1, wherein the constitution of the first resin composition is identical with that of the second resin composition, and the thickness of the first resin layer is different from that of the second resin layer, and

wherein a thickness of the sheet-shaped base member is 25 μ

m or less.

4. The prepreg as claimed in claim 2, wherein when the conductor layer is bonded to the first resin layer, peel strength between the first resin layer and the conductor layer is 0.5 kN/m or more.

5. The prepreg as claimed in claim 2, wherein the thickness of the first resin layer is in the range of 3 to 15 μ

m.

6. The prepreg as claimed in claim 2, wherein the first resin composition contains thermosetting resin.

7. The prepreg as claimed in claim 6, wherein the thermosetting resin contains cyanate resin.

8. The prepreg as claimed in claim 7, wherein the cyanate resin contains novolak type cyanate resin.

9. The prepreg as claimed in claim 2, wherein the first resin composition further contains a curing agent.

10. The prepreg as claimed in claim 9, wherein the curing agent contains an imidazole based compound.

11. The prepreg as claimed in claim 6, wherein the first resin composition further contains second resin whose kind is different from that of the thermosetting resin.

12. The prepreg as claimed in claim 11, wherein the second resin contains phenoxy based resin.

13. The prepreg as claimed in claim 2, wherein the thickness of the first resin layer is thiner than that of the second resin layer.

14. The prepreg as claimed in claim 3, wherein a thickness of the prepreg is 35 μ

m or less.

15. The prepreg as claimed in claim 3, wherein the resin composition contains thermosetting resin.

16. The prepreg as claimed in claim 15, wherein the thermosetting resin contains cyanate resin.

17. The prepreg as claimed in claim 3, wherein the resin composition further contains an inorganic filler.

18. A method for manufacturing the prepreg defined by claim 1, comprising;

preparing the core layer, a first sheet member having one surface on which the first resin composition is applied in the form of a layer, and a second sheet member having one surface on which the second resin composition is applied in the form of a layer;

laminating the core layer with the first sheet member and the second sheet member so that the first resin composition and the second resin composition make contact with both surfaces of the core layer, respectively, whereby the core layer, the first sheet member and the second sheet member are joined together to obtain a laminate; and

removing bubbles from the laminate.

19. The method as claimed in claim 18, wherein joining of the core layer, the first sheet member and the second sheet member is carried out under reduced pressure.

20. The method as claimed in claim 18, wherein removing of the bubbles from the laminate is carried out by a heat treatment.

21. The method as claimed in claim 20, wherein the heat treatment is carried out at a temperature of a melting point or higher, wherein the melting point is a higher melting point than a melting point of the first resin composition and a melting point of the second resin composition.

22. The method as claimed in claim 18, wherein the first sheet member is formed of a conductive material.

23. The method as claimed in claim 18, wherein each of the first sheet member and the second member is formed from a resin sheet, and

wherein the method further comprises after removing the bubbles from the laminate, removing the resin sheets from the laminate.

24. The method as claimed in claim 23, wherein a surface of each of the resin sheets on which each resin composition is applied is subjected to a release treatment.

25. A substrate, comprising;

the prepreg defined by claim 1; and

a circuit wiring portion embedded into the second resin layer of the prepreg.

26. The substrate as claimed in claim 25, wherein when a total thickness of the prepreg is defined by T0 μ

m and a height of the circuit wiring portion is defined by t1 μ

m, a difference of T0 and t1 is 35 μ

m or less.

27. The substrate as claimed in claim 25, wherein a thermal expansion coefficient of the prepreg in a plane direction thereof is 16 ppm or less.

28. A substrate manufactured by laminating a plurality of the prepregs each defined by claim 1.

29. A semiconductor device, comprising;

the substrate defined by claim 25; and

a semiconductor element mounted on the substrate.

30. A semiconductor device having the substrate defined by claim 28.