Spin Torque Transfer MTJ Devices with High Thermal Stability and Low Write Currents

• US 20090303779A1
• Filed: 06/05/2008
• Published: 12/10/2009
• Est. Priority Date: 06/05/2008
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Young-Shying, Wang, Yu-Jen, Wang, Yung-Hung, Lin, Chun-Jung
• Application Number:
  US12/133,865
• Publication Number:
  US 20090303779A1
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access

Abstract

An integrated circuit structure includes a first fixed magnetic element; a second fixed magnetic element; and a composite free magnetic element between the first and the second fixed magnetic elements. The composite free magnetic element includes a first free layer and a second free layer.

Claims

1. An integrated circuit structure comprising:

a first fixed magnetic element;

a second fixed magnetic element; and

a composite free magnetic element between the first and the second fixed magnetic elements, wherein the composite free magnetic element comprises a first free layer and a second free layer.

2. The integrated circuit structure of claim 1, wherein the first and the second fixed magnetic elements have parallel magnetization directions.

3. The integrated circuit structure of claim 1, wherein the first and the second free layers have anti-parallel magnetization directions.

4. The integrated circuit structure of claim 1, wherein the first fixed magnetic element comprises a first pinned sub layer, a second pinned sub layer, and a first coupling layer adjoining, and coupling magnetizations of, the first and the second pinned sub layers.

5. The integrated circuit structure of claim 4, wherein the second fixed magnetic element comprises a third pinned sub layer, a fourth pinned sub layer, and a second coupling layer adjoining, and coupling magnetizations of, the third and the fourth pinned sub layers.

6. The integrated circuit structure of claim 4, wherein the first fixed magnetic element further comprises a third pinned sub layer, and a second coupling layer adjoining, and coupling magnetizations of, the second and the third pinned sub layers.

7. The integrated circuit structure of claim 1 further comprising:

a conductive spacer between the first fixed magnetic element and the composite free magnetic element; and

a tunnel layer between the second fixed magnetic element and the composite free magnetic element.

8. The integrated circuit structure of claim 1 further comprising a coupling layer between the first and the second free layers, wherein the coupling layer is formed of a non-magnetic material.

9. An integrated circuit structure comprising:

a first fixed magnetic element;

a second fixed magnetic element, wherein the first and the second fixed magnetic elements have parallel magnetization directions;

a composite free magnetic element between the first and the second fixed magnetic elements, wherein the composite free magnetic element comprises a first free layer and a second free layer having anti-parallel magnetization directions;

a conductive spacer adjoining the first fixed magnetic element and the composite free magnetic element; and

a tunnel layer adjoining the second fixed magnetic element and the composite free magnetic element.

10. The integrated circuit structure of claim 9, wherein the composite free magnetic element further comprises a coupling layer between the first and the second free layers, wherein the coupling layer is formed of a non-magnetic material.

11. The integrated circuit structure of claim 10, wherein the coupling layer comprises a material selected from the group consisting essentially of Ru, Cu, and combinations thereof.

12. The integrated circuit structure of claim 9, wherein the conductive spacer comprises a non-magnetic material selected from the group consisting essentially of Ru, Cu, and combinations thereof.

13. The integrated circuit structure of claim 9, wherein the conductive spacer may be a low RA value of metal oxide or metal nitride.

14. The integrated circuit structure of claim 9, wherein the first fixed magnetic element comprises a first pinned sub layer and a second pinned sub layer, and a first coupling layer adjoining, and coupling magnetizations of, the first and the second pinned sub layers.

15. The integrated circuit structure of claim 14, wherein the second fixed magnetic element comprises a third pinned sub layer and a fourth pinned sub layer, and a second coupling layer adjoining, and coupling magnetizations of, the third and the fourth pinned sub layers.

16. The integrated circuit structure of claim 14, wherein the first fixed magnetic element further comprises a third pinned sub layer, and a second coupling layer adjoining, and coupling magnetizations of, the second and the third pinned sub layers.

17. The integrated circuit structure of claim 9 further comprising a first pinning layer adjoining the first fixed magnetic element, and a second pinning layer adjoining the second fixed magnetic element, wherein the first and the second pinning layers are formed of anti-ferro-magnetic materials.

18. An integrated circuit structure comprising:

a memory array comprising;

a magneto-resistive random access memory (MRAM) cell comprising;

a first fixed magnetic element;

a second fixed magnetic element;

a composite free magnetic element between the first and the second fixed magnetic elements, wherein the composite free magnetic element comprises a first free layer and a second free layer;

a conductive spacer adjoining the first fixed magnetic element and the composite free magnetic element; and

a tunnel layer adjoining the second fixed magnetic element and the composite free magnetic element;

a bit line electrically connected to a first end of the MRAM cell; and

a select transistor electrically connected to a second end of the MRAM cell.

19. The integrated circuit structure of claim 18 further comprising an additional select transistor having a gate connected to a word line, a source connected to a source line, and a drain connected to the second end of the MRAM cell.

20. The integrated circuit structure of claim 18, wherein the first and the second fixed magnetic elements have parallel magnetization directions, and wherein the first and the second free layers have anti-parallel magnetization directions.