COMBINING SIGNALS WITH A SHUFFLED-HADAMARD FUNCTION

• US 20090304048A1
• Filed: 06/09/2009
• Published: 12/10/2009
• Est. Priority Date: 12/05/2000
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Gunter, Michial Allen
• Granted Patent: US 8,374,218 B2
• Time in Patent Office: Days
• US Class Current: 375/145
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04J 13/10 Code generation
• CPC Class Codes: H04L 5/22 using time-division multiplexing

Abstract

A method can include receiving, at a transmitter, during a symbol time that comprises a plurality of chip times, a data value for each of a plurality of distinct data channel inputs. During each chip time, the method can include (a) indexing a different row of a matrix of data bits; (b) decoding one channel input using a first subset of one or more columns of the indexed row; (c) determining a code value for the decoded one channel from a second subset of one or more columns of the indexed row; and (d) providing the coded data value to a transmission circuit for transmission to a receiver. Actions (a) to (d) can be performed for each of the plurality of chip times in the symbol time. In some implementations, the matrix of data bits is a Hadamard matrix with randomly shuffled rows.

Claims

1. A computer-implemented method, comprising:

receiving, at a transmitter, during a symbol time that comprises a plurality of chip times, a data value for each of a plurality of distinct data channel inputs; and

during each chip time, (a) indexing a different row of a matrix of data bits, the matrix of data bits having a plurality of rows and a plurality of columns;

(b) decoding one channel from the plurality of distinct data channel inputs using a first subset of one or more columns of the indexed row;

(c) determining a code value for the decoded one channel from a plurality of possible code values that are derived from a second subset that is different than the first subset, the second subset comprising of one or more columns of the indexed row;

(d) providing the coded data value to a transmission circuit for transmission to a receiver; and

performing (a) to (d) for each of the plurality of chip times in the symbol time.

2. The method of claim 1, wherein the matrix of data bits comprises a first matrix that corresponds to a Hadamard matrix whose rows have been randomly or pseudo-randomly shuffled.

3. The method of claim 2, wherein the matrix of data bits comprises a compressed version of the first matrix having only columns with power-of-two indices from the matrix of data bits.

4. The method of claim 2, wherein data values received from the plurality of distinct data channel inputs and bits in the matrix of bits have binary values.

5. The method of claim 4, wherein the first subset comprises a number of columns corresponding to a base-2 logarithm of a number of data channel inputs in the plurality of distinct data channel inputs.

6. The method of claim 1, further comprising, at the receiver:

for each chip time in the symbol time, (e) receiving a bit from a medium that couples the receiver to the transmission circuit, (f) indexing a different row of the matrix of data bits, (g) decoding one channel from a plurality of distinct data channel outputs, which correspond to the plurality of distinct channel inputs at the transmitter, using the first subset of one or more columns of the indexed row, (h) comparing the received bit to each of the plurality of possible code values that are derived from the second subset; and

outputting, for the symbol time and based on performing (h) for a plurality of bits for each decoded channel, a data value for each of the distinct data channel outputs.

7. The method of claim 6, further comprising synchronizing (a) indexing in the transmitter and (f) indexing in the receiver.

8. The method of claim 1, wherein (c) determining the code value comprises determining the code value based on the data value.

9. The method of claim 8, wherein the data value is a binary value, and (c) determining the code value comprises selecting a different portion of one of two columns of the matrix of data bits for each chip time, the one of two columns being selected based on the data value.

10. The method of claim 8, wherein the data value has one of m possible predetermined values, and (c) determining the code value comprises selecting a different portion of one of m columns of the matrix of data bits for each chip time, the one of m columns being selected based on the data value.

11. The method of claim 1, wherein (c) determining the code value comprises applying a logical function to bits in two or more columns having power-of-two indices in the matrix of data bits.

12. A system comprising:

a transmitter comprising;

a plurality of data channel inputs that receive corresponding data channel input values during each symbol time, wherein each symbol time comprises a plurality of chip times;

a coder that codes each data channel input value with a corresponding data channel code value;

a multiplexer that selects a data channel code value for one of the data channel inputs during each chip time; and

transmit circuitry that transmits the selected data channel code value during each chip time to a receiver; and

a receiver comprising;

receive circuitry that receives data during each chip time, a demultiplexer that associates the received data with a particular data channel, a decoder that decodes data received during multiple chip times for each data channel, and a plurality data channel outputs that each provide decoded data for each data channel during a symbol time.

13. The system of claim 12, further comprising a controller that controls both the coder and the multiplexer based on a matrix of data bits.

14. The system of claim 13, wherein the controller controls the coder and multiplexer based on values in a different row of the matrix of data bits during each chip time.

15. The system of claim 13, wherein the matrix of data bits comprises a first matrix that is derived from a Hadamard matrix whose rows have been randomly or pseudo-randomly shuffled.

16. The system of claim 15, wherein the first matrix comprises only columns having power-of-two indices from the Hadamard matrix whose rows have been randomly or pseudo-randomly shuffled.

17. The system of claim 15, further comprising a transmitter counter and a receiver counter that are synchronized and incremented during a each chip time.

18. The system of claim 17, wherein the transmitter counter indexes a row in the matrix of bits, and during each chip time, a first portion of indexed row controls the coder and a second portion of the indexed row controls the multiplexer.

19. The system of claim 17, wherein the receiver counter indexes a row in the matrix of bits, and during each chip time, a first portion of the indexed row controls the demultiplexer.

20. The system of claim 12, wherein the receiver further comprises a plurality of correlators that are employed, over the course of each symbol time, by the decoder to decode received data for each data channel.

21. The system of claim 20, wherein the plurality of correlators calculate a correlation between received data and each of a plurality of possible data channel code values.