COMPACT MULTI-PORT CAM CELL IMPLEMENTED IN 3D VERTICAL INTEGRATION

• US 20090305462A1
• Filed: 08/17/2009
• Published: 12/10/2009
• Est. Priority Date: 05/18/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Robinson, Eric, Atwal, Jagreet S., Bucki, Robert J., Barnes, Joseph S., Bernstein, Kerry
• Granted Patent: US 8,343,814 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/821 Forming a build-up interconnect
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9212 Sequential connecting processes
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.

Claims

1. A method of forming a multi-ported CAM cell comprising:

providing a first wafer including a plurality of first transistors located upon and within a surface of a first active semiconductor layer;

providing a second wafer including a plurality of second transistors located upon and within a surface of a second active semiconductor layer;

first bonding a surface of said second wafer to a surface of said first wafer to provide a bonded structure in which the plurality of first transistors are located above the plurality of second transistors;

providing at least one other wafer including a plurality of other transistors located upon and within a surface of at least one other active semiconductor layer;

second bonding the at least one another wafer to a surface of said second wafer to provide another bonded structure in which each plurality of transistors are vertically stacked upon each other; and

forming at least one vertically filled conductive via to connect said plurality of transistors that are vertically stacked to each other.

2. The method of claim 1 wherein each of said wafers include a dielectric material having conductive filled openings that contact surfaces of said plurality of transistors.

4. The method of claim 1 wherein first bonding comprise bringing said first and second wafers into intimate contact with each other and bonding at a temperature that is about 20°

C. or greater.

5. The method of claim 1 wherein said at least one vertically filled conductive via is formed by first forming a via by lithography and etching and then filling the via with a conductive material.

6. The method of claim 1 wherein said plurality of first transistors and said plurality of other transistors each have a 9T configuration and said plurality of second transistors have a 6T configuration.

7. The method of claim 6 wherein said plurality of first transistors and said plurality of other transistors having said 9T configuration are located above said plurality of second transistors having said 6T configuration.

8. The method of claim 1 wherein said at least one vertically conductive filled via is aligned to conductive filled openings located within a dielectric material of said first wafer, said second wafer and said other wafers.

3. The method 1 wherein said providing said first wafer includes the steps of attaching a handling substrate to a surface of a dielectric material that encapsulates said plurality of first transistors.