MEMORY SYSTEM, MEMORY SYSTEM CONTROL METHOD, AND DRIVE RECORDER APPARATUS

• US 20090307414A1
• Filed: 02/24/2009
• Published: 12/10/2009
• Est. Priority Date: 06/04/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SUZUKI, Takashi, SUKEGAWA, Hiroshi
• Application Number:
  US12/391,583
• Publication Number:
  US 20090307414A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory system includes a NAND-type flash memory which includes a plurality of memory cells and can store one-bit, two-bit or more data in one memory cell, and a duplicating-converting circuit configured to duplicate input data by assigning the input data to a predetermined threshold level and another threshold level different from the predetermined threshold level. Moreover, the memory system includes a controller configured to control to store the data duplicated by the duplicating-converting circuit, in the NAND-type flash memory.

Claims

1. A memory system comprising:

a non-volatile memory including a plurality of memory cells which are controlled to be at any one of 2^m (m is a positive integer) kinds of threshold levels and thereby can retain m-bit data;

a duplicating-converting section configured to duplicate input data so that m-bit data to be retained in one of the memory cells are assigned to two threshold levels different from each other; and

a controller configured to write respective pieces of the input data duplicated by the duplicating-converting section, to memory areas different from each other in the non-volatile memory.

2. The memory system according to claim 1, wherein:

the duplicating-converting section codes the input data so that the m-bit data to be retained in one of the memory cells are assigned to two different threshold levels which have been cyclically shifted with respect to each other.

3. The memory system according to claim 2, wherein:

the memory cells are controlled to be at any one of a first threshold level, a second threshold level, a third threshold level, and a fourth threshold level in an order corresponding to a threshold voltage, and the controller can cause any one of first data, second data, third data and fourth data to correspond to each of the threshold levels; and

the duplicating-converting section includes a first series coding circuit configured to convert the input data so that the first data is assigned to the first threshold level, the second data is assigned to the second threshold level, the third data is assigned to the third threshold level, and the fourth data is assigned to the fourth threshold level, and a second series coding circuit configured to convert the input data so that the first data is assigned to the second threshold level, the second data is assigned to the third threshold level, the third data is assigned to the fourth threshold level, and the fourth data is assigned to the first threshold level.

4. The memory system according to claim 3, wherein:

the first series coding circuit converts the input data whether or not a control signal which is a trigger for duplicated storage is inputted; and

the second series coding circuit converts the input data only if the control signal is inputted.

5. The memory system according to claim 1, wherein:

the duplicating-converting section codes the input data so that the m-bit data to be retained in one of the memory cells are assigned to two different threshold levels which have been interchanged with each other between a high voltage application side and a low voltage application side.

6. The memory system according to claim 5, wherein:

the memory cells are controlled to be in four kinds of data states consisting of a first threshold level, a second threshold level, a third threshold level, and a fourth threshold level in an order corresponding to a threshold voltage, and the controller can cause any one of first data, second data, third data and fourth data to correspond to each of the threshold levels; and

the duplicating-converting section includes a first series coding circuit configured to convert the input data so that the first data is assigned to the first threshold level, the second data is assigned to the second threshold level, the third data is assigned to the third threshold level, and the fourth data is assigned to the fourth threshold level, and a second series coding circuit configured to convert the input data so that the first data is assigned to the fourth threshold level, the second data is assigned to the third threshold level, the third data is assigned to the second threshold level, and the fourth data is assigned to the first threshold level.

7. The memory system according to claim 6, wherein:

the first series coding circuit converts the input data whether or not a control signal which is a trigger for duplicated storage is inputted; and

the second series coding circuit converts the input data only if the control signal is inputted.

8. The memory system according to claim 1, further comprising:

an error correcting code circuit configured to attach an error correcting code to the respective pieces of the input data duplicated by the duplicating-converting section,

wherein the controller writes the respective pieces of the input data attached with the error correcting code, to the memory areas different from each other in the non-volatile memory.

9. The memory system according to claim 1, wherein:

the memory cells include a floating gate structure configured to retain the m-bit data by using a change in a threshold voltage of a transistor depending on the number of electrons injected into a floating gate electrode.

10. The memory system according to claim 1, wherein:

the memory cells include a MONOS structure configured to retain the m-bit data by using a change in a threshold voltage of a transistor depending on the number of electrons or holes trapped by a nitride film interface as a charge accumulation layer.

11. The memory system according to claim 1, wherein:

the non-volatile memory is a NAND-type flash memory or a NOR-type flash memory.

12. A memory system control method including a non-volatile memory including a plurality of memory cells which are controlled to be at any one of 2^m (m is a positive integer) kinds of threshold levels and thereby can retain m-bit data;

the memory system control method comprising;

duplicating input data so that m-bit data to be retained in one of the memory cells are assigned to two threshold levels different from each other; and

writing respective pieces of the duplicated input data to memory areas different from each other in the non-volatile memory.

13. The memory system control method according to claim 12, wherein:

the input data is coded so that the m-bit data to be retained in the one of the memory cells are assigned to two different threshold levels which have been cyclically shifted with respect to each other.

14. The memory system control method according to claim 13, wherein:

the memory cells are controlled to be at any one of a first threshold level, a second threshold level, a third threshold level, and a fourth threshold level in an order corresponding to a threshold voltage, and any one of first data, second data, third data and fourth data can be caused to correspond to each of the threshold levels;

first conversion of the input data is performed so that the first data is assigned to the first threshold level, the second data is assigned to the second threshold level, the third data is assigned to the third threshold level, and the fourth data is assigned to the fourth threshold level; and

second conversion of the input data is performed so that the first data is assigned to the second threshold level, the second data is assigned to the third threshold level, the third data is assigned to the fourth threshold level, and the fourth data is assigned to the first threshold level.

15. The memory system control method according to claim 14, wherein:

the first conversion of the input data is performed whether or not a control signal which is a trigger for duplicated storage is inputted; and

the second conversion of the input data is performed only if the control signal is inputted.

16. The memory system control method according to claim 12, wherein:

the input data is coded so that the m-bit data to be retained in the one of the memory cells are assigned to two different threshold levels which have been interchanged with each other between a high voltage application side and a low voltage application side.

17. The memory system control method according to claim 16, wherein:

the memory cells are controlled to be in four kinds of data states consisting of a first threshold level, a second threshold level, a third threshold level, and a fourth threshold level in an order corresponding to a threshold voltage, and any one of first data, second data, third data and fourth data can be caused to correspond to each of the threshold levels;

first conversion of the input data is performed so that the first data is assigned to the first threshold level, the second data is assigned to the second threshold level, the third data is assigned to the third threshold level, and the fourth data is assigned to the fourth threshold level; and

second conversion of the input data is performed so that the first data is assigned to the fourth threshold level, the second data is assigned to the third threshold level, the third data is assigned to the second threshold level, and the fourth data is assigned to the first threshold level.

18. The memory system control method according to claim 17, wherein:

the first conversion of the input data is performed whether or not a control signal which is a trigger for duplicated storage is inputted; and

the second conversion of the input data is performed only if the control signal is inputted.

19. The memory system control method according to claim 12, further comprising:

attaching an error correcting code to the respective pieces of the duplicated input data; and

writing the respective pieces of the input data attached with the error correcting code, to the memory areas different from each other in the non-volatile memory.

20. A drive recorder apparatus, comprising:

a moving image compressing section configured to compress input data from an image pickup apparatus, according to a predetermined scheme;

a volatile memory including a memory capacity capable of retaining the input data compressed by the moving image compressing section;

a shock sensor configured to output a control signal which is a trigger for duplicated storage when sensing an impact;

a non-volatile memory including a plurality of memory cells which are controlled to be at any one of 2^m (m is a positive integer) kinds of threshold levels and thereby can retain m-bit data;

a duplicating-converting section configured to duplicate the input data retained in the volatile memory so that m-bit data to be retained in one of the memory cells are assigned to two threshold levels different from each other; and

a controller configured to, when the control signal is outputted from the shock sensor, write respective pieces of the input data duplicated by the duplicating-converting section, to memory areas different from each other in the non-volatile memory.