METHOD OF FABRICATING COLLECTOR OF IGBT

• US 20090309130A1
• Filed: 06/12/2008
• Published: 12/17/2009
• Est. Priority Date: 06/12/2008
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Xu, Lin, Chen, Ju, Wang, CuiXia, Hsieh, Fu-Yuan
• Application Number:
  US12/137,539
• Publication Number:
  US 20090309130A1
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence

Abstract

The IGBT is described here that exhibits high breakdown voltage, low on-voltage together with high turn-off speed. The collector of IGBT is formed on the backside of the wafer which has n type float zone. Methods for the p-type collector is implemented by depositing a layer of BSG which is 0.05˜0.1 um on the backside of the wafer and removing it after short time deposition. A thin and high surface concentration p+ layer acts as P type collector of the IGBT is formed on the bottom surface of the wafer. The back metal electrode is sintered to form ohmic contact on the P type collector with high surface concentration. The hole injection efficiency is decreased with a thin layer p+ layer which hat means no P implantation is needed to form the collector and the speed performance of the IGBT is therefore improved.

Claims

1. A non-punch through IGBT device implemented in a float zone wafer, with a BSG layer deposited on the back side of said wafer to form the collector, comprising:

a float zone wafer having two parallel surfaces;

a DMOS structure formed in said float zone wafer;

a BSG layer deposited to form the collector and removed later.

2. The IGBT device of claim 1, wherein said float zone wafer has a concentration of 1E14 per cm³.

3. The IGBT device of claim 1, wherein after said DMOS structure is formed, thinning said wafer to its desired thickness, then depositing said BSG layer with boron dopant on the back surface of said wafer.

4. The IGBT device of claim 1, wherein said BSG layer has a thickness of 0.05˜

0.1 um and a concentration of 1E19˜

1E20 per cm.

5. The IGBT device of claim 1, wherein said BSG layer forms a P+ junction having a depth less than 0.1 um.

6. The BSG layer of claim 3, wherein no anneal process is needed to active the junction for the formation of P+ area after said BSG layer is deposited.

7. The BSG layer of claim 3, wherein said BSG layer will be removed after said deposition.