IMAGER DEVICES HAVING DIFFERING GATE STACK SIDEWALL SPACERS, METHOD FOR FORMING SUCH IMAGER DEVICES, AND SYSTEMS INCLUDING SUCH IMAGER DEVICES

• US 20090309142A1
• Filed: 06/11/2008
• Published: 12/17/2009
• Est. Priority Date: 06/11/2008
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman
• Granted Patent: US 8,129,764 B2
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00

Abstract

Imager devices have a sensor array and a peripheral region at least partially surrounding the sensor array. At least one transistor in the peripheral region has a gate stack sidewall spacer that differs in composition from a gate stack sidewall spacer on at least one transistor in the sensor array. Imaging systems include such an imager device configured to communicate electrically with at least one electronic signal processor and at least one memory storage device. Methods of forming such imager devices include providing layers of oxide and nitride materials over transistors on a workpiece, and using etching processes to form gate stack sidewall spacers on the transistors.

Claims

1. An imager device, comprising:

a sensor array comprising a plurality of array transistors substantially free of silicide material and each having gate stack sidewall spacers substantially free of nitride material; and

a peripheral region at least partially surrounding the sensor array, the peripheral region

comprising a plurality of peripheral transistors, each comprising;

at least one gate stack sidewall spacer comprising nitride material; and

silicide material on at least a portion of at least one of a gate, a source, and a drain of each respective peripheral transistor.

2. The imager device of claim 1, wherein the peripheral region substantially entirely surrounds the sensor array.

3. The imager device of claim 1, wherein the array transistors each have gate stack sidewall spacers comprising an oxide material.

4. The imager device of claim 3, wherein the array transistors each have gate stack sidewall spacers predominantly comprised of silica (SiO₂).

5. The imager device of claim 1, wherein the peripheral transistors of the plurality each comprise at least one gate stack sidewall spacer having a first region comprising a nitride material and a second region comprising an oxide material.

6. The imager device of claim 5, wherein the nitride material is disposed between the oxide material and at least a portion of a gate.

7. The imager device of claim 6, wherein the at least a portion of the gate comprises the silicide material.

8. The imager device of claim 6, wherein the nitride material is disposed between the oxide material and at least a portion of at least one of a source and a drain.

9. The imager device of claim 7, wherein the at least a portion of at least one of a source and a drain comprises the silicide material.

10. The imager device of claim 5, wherein the first region is predominantly comprised of silicon nitride (Si₃N₄) and the second region is predominantly comprised of silica (SiO₂).

11. The imager device of claim 1, wherein the silicide material comprises at least one of cobalt silicide (CoSi₂), titanium silicide (TiSi₂), and nickel silicide (NiSi₂).

12. An imager device comprising:

a sensor array comprising a plurality of pixel circuits, each comprising at least one photosensitive element and at least one array transistor, the at least one array transistor being substantially free of nitride material and silicide material; and

at least one logic circuit located laterally adjacent the sensor array, the at least one logic circuit comprising a plurality of peripheral transistors, at least one peripheral transistor of the plurality comprising;

at least one gate stack sidewall spacer comprising nitride material; and

silicide material on at least a portion of at least one of a gate, a source, and a drain of the at least one peripheral transistor.

13. The imager device of claim 12, wherein the at least one logic circuit is disposed in a peripheral region of the imager device.

14. The imager device of claim 13, wherein the at least one logic circuit comprises at least a portion of at least one of a row decoder, a column decoder, a controller, an analog-to-digital converter, and a pixel processor of the imager device.

15. The imager device of claim 12, wherein the at least one photosensitive element comprises a photodiode.

16. The imager device of claim 12, wherein the at least one array transistor comprises one of a charge transfer transistor, a reset transistor, a source follower transistor, and a row select transistor.

17. The imager device of claim 12, wherein the at least one array transistor comprises at least one gate stack sidewall spacer substantially comprised of an oxide material.

18. The imager device of claim 12, wherein the at least one peripheral transistor comprises at least one gate stack sidewall spacer having a first region comprising a nitride material and a second region comprising an oxide material.

19. The imager device of claim 18, wherein the nitride material is disposed between the oxide material and at least a portion of a gate of the at least one peripheral transistor.

20. The imager device of claim 19, wherein the at least a portion of the gate comprises the silicide material.

21. The imager device of claim 18, wherein the nitride material is disposed between the oxide material and at least a portion of at least one of a source and a drain.

22. The imager device of claim 21, wherein the at least a portion of at least one of a source and a drain comprises the silicide material.

23. The imager device of claim 18, wherein the first region is predominantly comprised of silicon nitride (Si₃N₄) and the second region is predominantly comprised of silica (SiO₂).

24. The imager device of claim 12, wherein the silicide material comprises at least one of cobalt silicide (CoSi₂), titanium silicide (TiSi₂), and nickel silicide (NiSi₂).

25. An imaging system for capturing an electronic representation of an image, the imaging system comprising:

at least one electronic signal processor;

at least one memory storage device; and

at least one imager device configured to communicate electrically with the at least one signal processor and the at least one memory storage device, the at least one imager device comprising;

a sensor array comprising a plurality of array transistors substantially free of silicide material and each having gate stack sidewall spacers substantially free of nitride material; and

a peripheral region at least partially surrounding the sensor array, the peripheral region comprising a plurality of peripheral transistors, each comprising;

at least one gate stack sidewall spacer comprising nitride material; and

silicide material on at least a portion of at least one of a gate, a source, and a drain of each respective peripheral transistor.

26. The imaging system of claim 25, wherein the imaging system comprises at least one of a digital camera, a cellular telephone, a computer, and a personal digital assistant (PDA).

27. The imaging system of claim 25, wherein the peripheral transistors of the plurality each comprise at least one gate stack sidewall spacer having a first region comprising a nitride material and a second region comprising an oxide material.

28. The imaging system of claim 27, wherein the nitride material is disposed between the oxide material and at least a portion of a gate comprising the silicide material.

29. The imaging system of claim 27, wherein the nitride material is disposed between the oxide material and at least a portion of at least one of a source and a drain comprising the silicide material.

30. The imaging system of claim 27, wherein the first region is predominantly comprised of silicon nitride (Si₃N₄) and the second region is predominantly comprised of silica (SiO₂).

31. An imaging system for capturing an electronic representation of an image, the imaging system comprising:

at least one electronic signal processor;

at least one memory storage device; and

at least one imager device configured to communicate electrically with the at least one signal processor and the at least one memory storage device, the at least one imager device comprising;

a sensor array comprising a plurality of pixel circuits, each comprising at least one photosensitive element and at least one array transistor, the at least one array transistor being substantially free of nitride material and silicide material; and

at least one logic circuit located laterally beside the sensor array, the at least one logic circuit comprising a plurality of peripheral transistors, at least one peripheral transistor of the plurality comprising;

at least one gate stack sidewall spacer comprising nitride material; and

silicide material on at least a portion of at least one of a gate, a source, and a drain of the at least one peripheral transistor.

32. The imaging system of claim 31, wherein the imaging system comprises at least one of a digital camera, a cellular telephone, a computer, and a personal digital assistant (PDA).

33. The imaging system of claim 31, wherein the at least one logic circuit is disposed in a peripheral region of the imager device and comprises at least a portion of at least one of a row decoder, a column decoder, a controller, an analog-to-digital converter, and a pixel processor of the imager device.

34. The imaging system of claim 31, wherein the at least one array transistor comprises one of a charge transfer transistor, a reset transistor, a source follower transistor, and a row select transistor.

35. The imaging system of claim 31, wherein the at least one peripheral transistor comprises at least one gate stack sidewall spacer having a first region comprising a nitride material and a second region comprising an oxide material.

36. The imaging system of claim 35, wherein the nitride material is disposed between the oxide material and at least a portion of a gate of the at least one peripheral transistor comprising the silicide material.

37. The imaging system of claim 35, wherein the nitride material is disposed between the oxide material and at least a portion of at least one of a source and a drain comprising the silicide material.

38. The imaging system of claim 35, wherein the first region is predominantly comprised of silicon nitride (Si₃N₄) and the second region is predominantly comprised of silica (SiO₂).

39. A method of forming at least one imager device, the method comprising:

providing a layer of nitride material at least over a portion of a peripheral region of at least one partially formed imager device on a workpiece;

etching the layer of nitride material to form at least a portion of at least one nitride gate stack sidewall spacer on at least one peripheral transistor in the peripheral region;

providing a layer of oxide material over at least a portion of a sensor array of the at least one partially formed imager device;

etching the layer of oxide material to form at least a portion of at least one oxide gate stack sidewall spacer on at least one array transistor in the at least a portion of the sensor array; and

causing the at least one array transistor to be substantially free of nitride material.

40. The method of claim 39, wherein providing the layer of nitride material comprises:

depositing the layer of nitride material over the workpiece; and

selectively removing at least one portion of the layer of nitride material overlying the sensor array of the at least one partially formed imager device.

41. The method of claim 39, wherein providing the layer of oxide material comprises providing the layer of oxide material prior to etching the layer of nitride material to form at least a portion of at least one nitride gate stack sidewall spacer.

42. The method of claim 39, wherein providing the layer of oxide material comprises providing the layer of oxide material after etching the layer of nitride material to form at least a portion of at least one nitride gate stack sidewall spacer.

43. The method of claim 39, wherein providing the layer of oxide material comprises depositing the layer of oxide material over both the peripheral region and the sensor array of the at least one partially formed imager device on the workpiece.

44. The method of claim 43, wherein etching the layer of oxide material comprises forming at least a portion of at least one oxide gate stack sidewall spacer on each of at least one peripheral transistor in the peripheral region and at least one array transistor in the sensor array.

45. The method of claim 44, further comprising disposing the at least one nitride gate stack sidewall spacer between the oxide gate stack sidewall spacer on the at least one peripheral transistor and a gate of the at least one peripheral transistor.

46. The method of claim 44, further comprising disposing the at least one nitride gate stack sidewall spacer between the oxide gate stack sidewall spacer on the at least one peripheral transistor and at least one of a source and a drain of the at least one peripheral transistor.

47. The method of claim 39, wherein providing a layer of nitride material comprises providing a layer of silicon nitride (Si₃N₄).

48. The method of claim 39, wherein providing a layer of oxide material comprises providing a layer of silica (SiO₂).

49. The method of claim 39, further comprising providing silicide material on at least one of a gate, a source, and a drain of the at least one peripheral transistor in the peripheral region.

50. The method of claim 49, wherein providing silicide material comprises providing at least one of cobalt silicide (CoSi₂), titanium silicide (TiSi₂), and nickel silicide (NiSi₂).

51. The method of claim 39, further comprising forming an anti-reflective coating in the sensor array from the layer of nitride material.

52. An imager device, comprising:

a sensor array comprising a plurality of array transistors, at least one array transistor of the plurality having at least one gate stack sidewall spacer substantially free of nitride material; and

a peripheral region at least partially surrounding the sensor array, the peripheral region comprising a plurality of peripheral transistors, at least one peripheral transistor of the plurality having at least one gate stack sidewall spacer comprising nitride material.

53. The imager device of claim 52, wherein the at least one array transistor of the plurality is substantially free of silicide material.

54. The imager device of claim 53, wherein the at least one peripheral transistor of the plurality comprises a silicide material on at least a portion of at least one of a gate, a source, and a drain of the at least one peripheral transistor.