Integrated Circuits Having a Contact Region and Methods for Manufacturing the Same
First Claim
1. An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising:
- a fin structure extending in a first direction, the fin structure comprising;
a first memory cell structure comprising a plurality of first active regions of a first plurality of memory cells coupled with each other in serial connection in the first direction;
a second memory cell structure comprising a plurality of second active regions of a second plurality of memory cells coupled with each other in serial connection in the first direction, wherein the second memory cell structure is disposed above the first memory cell structure; and
a memory cell contact structure configured to electrically couple the first memory cell structure and the second memory cell structure, wherein the memory cell contact structure has a staircase structure, a first step of which is configured to electrically contact the first memory cell structure, and a second step of which is configured to electrically contact the second memory cell structure.
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Accused Products
Abstract
In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
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Citations
25 Claims
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1. An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising:
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a fin structure extending in a first direction, the fin structure comprising; a first memory cell structure comprising a plurality of first active regions of a first plurality of memory cells coupled with each other in serial connection in the first direction; a second memory cell structure comprising a plurality of second active regions of a second plurality of memory cells coupled with each other in serial connection in the first direction, wherein the second memory cell structure is disposed above the first memory cell structure; and a memory cell contact structure configured to electrically couple the first memory cell structure and the second memory cell structure, wherein the memory cell contact structure has a staircase structure, a first step of which is configured to electrically contact the first memory cell structure, and a second step of which is configured to electrically contact the second memory cell structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising:
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a fin structure, comprising; a first memory cell structure having at least one first active region of at least one first memory cell; a second memory cell structure having at least one second active region of at least one second memory cell, wherein the second memory cell structure is disposed above the first memory cell structure; and a memory cell contact structure configured to electrically couple the first memory cell structure and the second memory cell structure, wherein the memory cell contact structure has a staircase structure, a first step of which is configured to electrically contact the first memory cell structure, and a second step of which is configured to electrically contact the second memory cell structure. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising:
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a substrate; a fin structure disposed above the substrate, the fin structure comprising; a memory cell region comprising a plurality of memory cell structures being disposed above one another, each memory cell structure comprising an active region of a respective memory cell; and a memory cell contacting region configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region comprises a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to a main processing surface of the substrate. - View Dependent Claims (20, 21, 22, 23)
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24. A method for manufacturing an integrated circuit comprising a memory cell arrangement, the method comprising:
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forming a fin structure; forming a memory cell region in the fin structure, the memory cell region comprising a plurality of memory cell structures disposed above one another, each memory cell structure comprising an active region of a respective memory cell; and forming a memory cell contacting region configured to electrically contact each of the memory cell structures, such that the memory cell contacting region comprises a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to a main processing surface of the substrate.
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25. A method for manufacturing an integrated circuit comprising a memory cell arrangement, the method comprising:
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forming a fin structure such that the fin structure comprises a first memory cell structure having at least one first active region of at least one first memory cell in the fin structure, and a second memory cell structure having at least one second active region of at least one second memory cell, wherein the second memory cell structure is disposed above the first memory cell structure; and forming a memory cell contact structure configured to electrically couple the first memory cell structure and the second memory cell structure, such that the memory cell contact structure has a staircase structure, a first step of which is configured to electrically contact the first memory cell structure, and a second step of which is configured to electrically contact the second memory cell structure.
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Specification