Method and Apparatus for Wafer Level Integration Using Tapered Vias

• US 20090309235A1
• Filed: 06/11/2008
• Published: 12/17/2009
• Est. Priority Date: 06/11/2008
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Marimuthu, Pandi Chelvam, Suthiwongsunthorn, Nathapong
• Granted Patent: US 7,863,721 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13118 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer.

Claims

1. A method of making a semiconductor device, comprising:

providing a first wafer having a bond pad formed over a front surface of the first wafer;

providing a second wafer having a bond pad formed over a front surface of the second wafer;

connecting the bond pads of the first and second wafers using a conductive adhesive;

forming a first interconnect structure within the second wafer by,

forming a first via in a back surface of the second wafer opposite the front surface, the first via exposing the bond pad of the second wafer, and

forming a first metal layer conformally over the first via, the first metal layer being in electrical contact with the bond pad of the second wafer;

mounting a third wafer over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer; and

forming a second interconnect structure over a backside of the third wafer opposite the front surface, the second interconnect structure being electrically connected to the first metal layer.

2. The method of claim 1, including disposing adhesive material between the first and second wafers.

3. The method of claim 1, including forming a through silicon via (TSV) in a back surface of the second wafer, the TSV having a conical frustum shape.

4. The method of claim 1, including depositing passivation over the first metal layer.

5. The method of claim 4, wherein the passivation is deposited as a conformal coating.

6. The method of claim 1, wherein the second interconnect structure includes a plurality of solder bumps.

7. The method of claim 6, including connecting the second interconnect structure to a printed circuit board (PCB) by reflowing the solder bumps.

8. A method of making a semiconductor device, comprising:

providing a first wafer having a bond pad formed over a front surface of the first wafer;

providing a second wafer having a bond pad formed over a front surface of the second wafer;

connecting the bond pads of the first and second wafers using a conductive adhesive;

forming a first interconnect structure within the second wafer;

mounting a third wafer over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first interconnect structure; and

forming a second interconnect structure over a backside of the third wafer opposite the front surface, the second interconnect structure being electrically connected to the first interconnect structure.

9. The method of claim 8, wherein forming the first interconnect structure includes:

forming a first via in a back surface of the second wafer opposite the front surface, the first via exposing the bond pad of the second wafer; and

forming a first metal layer over the first via, the first metal layer being in electrical contact with the bond pad of the second wafer.

10. The method of claim 8, including disposing adhesive material between the first and second wafers.

11. The method of claim 8, including forming a through silicon via (TSV) in a back surface of the second wafer, the TSV having a conical frustum shape.

12. The method of claim 8, including depositing passivation over the first interconnect structure.

13. The method of claim 12, wherein the passivation is deposited as a conformal coating.

14. The method of claim 8, wherein the second interconnect structure includes a plurality of solder bumps.

15. The method of claim 14, including connecting the second interconnect structure to a printed circuit board (PCB) by reflowing the solder bumps.

16. A method of making a semiconductor device, comprising:

providing a first wafer having a bond pad formed over a front surface of the first wafer;

providing a second wafer having a bond pad formed over a front surface of the second wafer;

connecting the bond pads of the first and second wafers using a conductive adhesive; and

forming a first interconnect structure within the second wafer by,

forming a first via in a back surface of the second wafer opposite the front surface, the first via exposing the bond pad of the second wafer, and

forming a first metal layer over the first via, the first metal layer being in electrical contact with the bond pad of the second wafer.

17. The method of claim 16, including:

mounting a third wafer over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first interconnect structure; and

forming a second interconnect structure over a backside of the third wafer opposite the front surface, the second interconnect structure being electrically connected to the first interconnect structure.

18. The method of claim 16, including forming a through silicon via (TSV) in a back surface of the second wafer, the TSV having a conical frustum shape.

19. The method of claim 17, wherein the second interconnect structure includes a plurality of solder bumps.

20. The method of claim 19, including connecting the second interconnect structure to a printed circuit board (PCB) by reflowing the solder bumps.

21. A semiconductor device, comprising:

a first wafer having a bond pad formed over a front surface of the first wafer;

a second wafer having a bond pad formed over a front surface of the second wafer, the bond pad of the second wafer being connected to the bond pad of the first wafer using a conductive adhesive;

a first interconnect structure formed within the second wafer, the first interconnect structure including,

a first via formed in a back surface of the second wafer opposite the front surface, the first via exposing the bond pad of the second wafer, and

a first metal layer formed conformally over the first via, the first metal layer being in electrical contact with the bond pad of the second wafer;

a third wafer mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer; and

a second interconnect structure formed over a backside of the third wafer opposite the front surface, the second interconnect structure being electrically connected to the first metal layer.

22. The semiconductor device of claim 21, including a through silicon via (TSV) formed in a back surface of the second wafer, the TSV having a conical frustum shape.

23. The semiconductor device of claim 21, wherein the second interconnect structure includes a plurality of solder bumps.

24. The semiconductor device of claim 23, including a printed circuit board (PCB) connected to a plurality of solder bumps of the second interconnect structure.

25. The semiconductor device of claim 21, including a passivation layer deposited over the first metal layer, the passivation layer being deposited as a conformal coating.