Phase Alignment Circuit for a TDC in a DPLL
First Claim
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1. Electronic circuitry comprising a phase alignment circuit and a digital controlled oscillator (DCO) and a frequency divider, the electronic circuitry configured to:
- use the phase alignment circuit to determine a phase relationship between a first signal and a second signal, the second signal derived by dividing an output signal provided by the DCO;
use the phase alignment circuit to disable operation of the frequency divider in accordance with the determination, the state of the frequency divider being preserved during the disabling; and
use the phase alignment circuit enable operation of the frequency divider in response to a next rising edge of the first signal, the frequency divider counting toward a predetermined state, the frequency divider providing an output pulse whenever the frequency divider reaches the predetermined state.
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Abstract
The present disclosure relates to circuits and methods for accelerating a new frequency lock-in process of a digital phase-locked loop.
11 Citations
20 Claims
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1. Electronic circuitry comprising a phase alignment circuit and a digital controlled oscillator (DCO) and a frequency divider, the electronic circuitry configured to:
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use the phase alignment circuit to determine a phase relationship between a first signal and a second signal, the second signal derived by dividing an output signal provided by the DCO; use the phase alignment circuit to disable operation of the frequency divider in accordance with the determination, the state of the frequency divider being preserved during the disabling; and use the phase alignment circuit enable operation of the frequency divider in response to a next rising edge of the first signal, the frequency divider counting toward a predetermined state, the frequency divider providing an output pulse whenever the frequency divider reaches the predetermined state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A phase alignment circuit configured to:
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receive a first signal corresponding to a phase relationship between a reference frequency signal and a divided-by-N digital controlled oscillator output signal; provide a first level output signal responsive to a predetermined state of the first signal, the first level output signal configured to disable operation of a frequency divider; and provide a second level output signal responsive to a next rising edge of the reference frequency signal, the second level output signal configured to enable operation of the frequency divider. - View Dependent Claims (10, 11)
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12. A method performed at least in part by an electronic circuit, the method comprising:
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measuring a phase relationship between a reference frequency signal and a divided-by-N digital controlled oscillator output signal; disabling operation of a frequency divider in accordance with the measuring, the present state of the frequency divider being preserved during the disabling; enabling operation of the frequency divider in response to a next rising edge of the reference frequency signal, the frequency divider counting toward a predetermined state; and providing an output pulse in response to the frequency divider reaching the predetermined state. - View Dependent Claims (13, 14, 15, 16)
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17. An electronic circuit, comprising:
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a first circuit portion including at least one flip-flip, the first circuit portion configured to provide an internal enable/disable signal responsive to a first enable signal and a second enable signal and a first clock signal, the first clock signal corresponding to a divided-by-N digital controlled oscillator output signal; a second circuit portion including a selector, the second circuit portion configured to provide a second clock signal responsive to reference clock input signal and an inverted reference input signal; and a third circuit portion including at least two other flip-flops, the third circuit portion configured to provide a frequency divider enable/disable signal responsive to the internal enable/disable signal and the second clock signal and a third clock signal, the third clock signal corresponding to a phase relationship between a reference frequency signal and the divided-by-N digital controlled oscillator output signal. - View Dependent Claims (18)
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19. An apparatus, comprising:
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a source of electrical energy; and a circuit coupled to the source of electrical energy, the circuit including a digital phase-locked loop and a phase alignment circuit, the phase alignment circuit configured to controllably enable and disable a frequency divider of the digital phase-locked loop during a frequency lock-in procedure. - View Dependent Claims (20)
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Specification