APPARATUS AND METHOD FOR SELECTABLE HARDWARE ACCELERATORS IN A DATA DRIVEN ARCHITECTURE

• US 20090309884A1
• Filed: 08/26/2009
• Published: 12/17/2009
• Est. Priority Date: 06/23/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lippincott, Louis A., Johnson, Patrick F.
• Granted Patent: US 8,063,907 B2
• Time in Patent Office: Days
• US Class Current: 345/502
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit.

Claims

1. A method comprising:

enabling a hardware accelerator selected from a plurality of hardware accelerators in response to a control command written by a processing element of a plurality of processing elements of a media signal processor to identify and request ownership of the selected hardware accelerator; and

granting the processing element ownership over the selected hardware accelerator, the selected hardware accelerator to perform a media processing function according to the control command to provide a data driven media architecture.

2. The method of claim 1, wherein enabling the selected hardware accelerator comprises:

enabling a processing element to set a bit when the process desires selection of a hardware accelerator; and

activating the selected hardware accelerator if the bit is set.

3. The method of claim 1, wherein enabling the selected hardware accelerator comprises:

designating at least one register within the register file to receive control commands from the plurality of processing elements; and

activating the selected hardware accelerator to perform a media processing function according to a control command detected within the register.

4. The method of claim 1, further comprising:

providing a selection unit coupled to the plurality of hardware accelerators;

designating at least one register within the register file to receive control commands from the plurality of processing elements;

directing the selection unit to provide a processing element with access to a selected hardware accelerators; and

directing the selecting hardware accelerator to perform a media processing function according to a received control command.

5. The method of claim 3, wherein activating the selected hardware accelerator comprises:

identifying a processing element having written the control command;

determining, according to the control command, an input data stream for the selected hardware accelerator;

determining, according to the control command, an output data stream for the selected hardware accelerator;

directing the selecting hardware accelerator to perform a media processing function according to a received control command;

updating a control bit within a register of the register file to indicate whether data is available for one or more data dependent processing elements; and

requiring the one or more data dependent processing elements to wait to execute instructions until the data it needs to execute the instructions is available in one or more registers.

12. The processor of claim 1, wherein the plurality of processing elements comprise:

an input processing element coupled to said register file, the input processing element to receive input data; and

an output processing element coupled to the register file, the output processing element to transmit data.

6. A machine-readable storage medium storing instructions, which when accessed by the computer result in the computer performing a method, comprising:

enabling a hardware accelerator selected from a plurality of hardware accelerators in response to a control command written by a processing element to identify and request ownership of the selected hardware accelerator; and

granting the processing element ownership over the selected hardware accelerator, the selected hardware accelerator to perform a media processing function according to the detected control command to provide a data driven media architecture.

7. The machine-readable storage medium of claim 6, wherein enabling the selected hardware accelerator comprises:

enabling a processing element to set a bit when the process desires selection of a hardware accelerator; and

activating the selected hardware accelerator if the bit is set.

8. The machine-readable storage medium of claim 6, wherein the enabling the selected hardware accelerator further comprises:

designating at least one register within the register file to receive control commands from the plurality of processing elements; and

activating the selected hardware accelerator to perform a media processing function according to a control command detected within the register.

9. The machine-readable storage medium of claim 6, wherein the method further comprises:

providing a selection unit coupled to the plurality of hardware elements;

designating at least one register within the register file to receive control commands from the plurality of processing elements;

directing the selection unit to provide a processing element with access to a selected hardware element; and

directing the selecting hardware accelerator to perform a media processing function according to a received control command.

10. The machine-readable storage medium of claim 8, wherein activating the selected hardware accelerator further comprises:

identifying a processing element having written the control command;

determining, according to the control command, an input data stream for the selected hardware accelerator;

determining, according to the control command, an output data stream for the selected hardware accelerator;

directing the selecting hardware accelerator to perform a media processing function according to a received control command;

updating a control bit within a register of the register file to indicate whether data is available for one or more data dependent processing elements; and

requiring the one or more data dependent processing elements to wait to execute instructions until the data it needs to execute the instructions is available in one or more registers.

11. A processor, comprising:

a plurality of processing elements;

a plurality of hardware accelerators coupled to a selection unit; and

a register file coupled to the selection unit, the selection unit to allow a processing element to identify and request ownership of a hardware accelerator in response to a control command within the register file, written by a processing element when the processing element desires ownership of the selected hardware accelerator; and

a control unit to direct the selection unit to activate the selected hardware accelerator to grant the processing element ownership over the selected hardware accelerator, the selected hardware accelerator to perform a media processing function according to the detected control command to provide a data driven media architecture.

13. The processor of claim 11, wherein the section unit to receive a control command from a processing element within at least one register of the register file, and activate the selected hardware accelerator to perform a media processing function according to the received control command.

14. The processor of claim 11, wherein the control unit to identify a processing element having written a control command, and set a control bit within a register of the register file to indicate when data is available for the identified processing element from the selected hardware accelerator.

15. The processor of claim 11, wherein a processing element to set a bit when the processing element desires selection of a hardware accelerator and set one more bits to identify one or more data dependent processing elements to prevent the identified processing elements from executing instructions until the one or more bits are reset.

16. The processor of claim 11, wherein the processing element to write a control command to a at least one register within the register file to direct a selected hardware accelerator to perform a media processing function according to the control command and set a control bit to indicate the selected hardware accelerator is in use.

17. The processor of claim 11, wherein a processing element to set one or more control bits within a register of the register file to identify one or more data dependent processing elements to stall the identified processing elements and prohibit execution of instructions until data required by the identified processing elements is available in one or more registers.

18. The processor of claim 11, wherein the hardware accelerators comprise image processing hardware accelerators.

19. The processor of claim 11, wherein the hardware accelerators comprise video processing hardware accelerators.

20. The processor of claim 11, wherein the hardware accelerators comprise audio processing hardware accelerators.

21. A system comprises:

a plurality of media signal processors coupled together via input and output ports to enable data exchange between each media signal processor, the media signal processors including;

a plurality of processing elements;

a plurality of hardware accelerators coupled to a selection unit;

a register file coupled to the selection unit, the selection unit to allow a processing element to identify and request ownership of a selected hardware accelerator;

a control unit coupled to the selection unit to direct the selection unit to activate the selected hardware accelerator in response to a control command detected written by a processing element when the processing element desires ownership of the selected hardware accelerator to grant the processing element ownership over the selected hardware accelerator;

a memory interface coupled to one or more of the media processors; and

a random access memory coupled to the memory interface, the selected hardware accelerator to perform a media processing function according to the control command to provide a data driven media architecture.

22. The system of claim 21, wherein the section unit to receive a control command from a processing element within at least one register of the register file, and activate the selected hardware accelerator to perform a media processing function according to the received control command.

23. The system of claim 21, wherein the control unit to identify a processing element having written a control command and set a control bit within a register of the register file to indicate when data is available for the identified processing element from the selected hardware accelerator.

24. The system of claim 21, wherein a processing element to set a bit when the processing element desires selection of a hardware accelerator and set bits corresponding to one or more data dependent processing elements to prevent the identified processing elements from executing instructions until the one or more bits are reset.

25. The system of claim 21, wherein the processing element to write a control command to a at least one register within the register file to direct a selected hardware accelerator to perform a media processing function according to the written control command and set a control bit to indicate a hardware accelerator is in use.

26. The system of claim 21, wherein a processing element to set one or more control bits within a register of the register file to identify one or more data dependent processing elements to stall the identified processing elements and prohibit execution of an instructions until data required by identified processing elements is available in one or more registers.

27. The system of claim 21, wherein the random access memory (RAM) is a synchronous data random access memory (SDRAM).

28. The system of claim 27, wherein the SDRAM is a double data rate (DDR) SDRAM.