Memory system and method of accessing a semiconductor memory device
First Claim
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1. A nonvolatile memory device comprising:
- a memory cell array including a plurality of multi-level cells; and
a control unit configured to determine a characteristic of data to be stored in the memory cell array,wherein the control unit is configured to select one of plural multi-bit programming methods with based on the determination,wherein data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit (LSB) data when there is a program fail of most significant bit (MSB) data.
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Abstract
A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.
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Citations
21 Claims
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1. A nonvolatile memory device comprising:
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a memory cell array including a plurality of multi-level cells; and a control unit configured to determine a characteristic of data to be stored in the memory cell array, wherein the control unit is configured to select one of plural multi-bit programming methods with based on the determination, wherein data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit (LSB) data when there is a program fail of most significant bit (MSB) data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A nonvolatile memory device comprising:
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a flash memory device including a memory cell array including a plurality of multi-level cells; and a memory controller configured to control the flash memory device to program the multi-level cells by one of plural multi-bit programming methods with reference to a characteristic of data to be stored, wherein at least one of the plural multi-bit programming methods maintains least significant bit (LSB) data when there is a program fail with most significant bit (MSB) data. - View Dependent Claims (17, 18, 19)
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20. A programming method of a nonvolatile memory device, comprising:
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selecting one of a plurality of multi-bit programming methods with reference to a characteristic of data to be stored; and storing data in a memory cell array using the selected multi-bit programming method, at least one of the plurality of multi-bit programming methods maintaining least significant bit (LSB) data when there is a program fail of most significant bit (MSB) data, wherein the plural multi-bit programming methods include first and second multi-bit programming methods, the first multi-bit programming method is selected if an address of the data to be stored is correspondent with a first area of the memory cell array and the second multi-bit programming method is selected if the address of the data to be stored is correspondent with a second area of the memory cell array.
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21-128. -128. (canceled)
Specification