Memory system and method of accessing a semiconductor memory device

• US 20090310408A1
• Filed: 06/12/2009
• Published: 12/17/2009
• Est. Priority Date: 06/13/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shim, Hojun, Song, Je-Hyuck, Roh, Kangho, Kim, Seontaek, Lee, Yang-sup, Cho, Wonhee, Park, Jong Tae, Lee, Jaesoo, Cheon, Wonmoon, Cho, Seung-Duk, Heo, Jaehoon, Choi, Youngjoon, Park, Chanik, Oh, Moonwook
• Granted Patent: US 8,027,194 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Claims

1. A nonvolatile memory device comprising:

a memory cell array including a plurality of multi-level cells; and

a control unit configured to determine a characteristic of data to be stored in the memory cell array,

wherein the control unit is configured to select one of plural multi-bit programming methods with based on the determination,

wherein data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit (LSB) data when there is a program fail of most significant bit (MSB) data.

2. The nonvolatile memory device as set forth in claim 1, wherein

the plural multi-bit programming methods include first and second multi-bit programming methods,

the control unit is configured to select the first multi-bit programming method as the selected multi-bit programming method if an address of the data to be stored is correspondent with a first area of the memory cell array, and the control unit is configured to select the second multi-bit programming method as the selected multi-bit programming method if the address of the data to be stored is correspondent with a second area of the memory cell array.

3. The nonvolatile memory device as set forth in claim 2, wherein the first area is a data area and the second area is a reserved area for correcting the data area.

4. The nonvolatile memory device as set forth in claim 2, wherein in programming the MSB data by the second multi-bit programming method, the programming is carried out for another data state after programming for a data state.

5. The nonvolatile memory device as set forth in claim 4, wherein in conducting a programming operation by the second multi-bit programming method a first data state is programmed after programming the LSB data;

a second data state is programmed after programming the first data sate; and

a third data state is programmed after programming the second data state.

6. The nonvolatile memory device as set forth in claim 5, wherein the first data state corresponds to a highest threshold voltage state, the second data state corresponds to a threshold voltage state lower than the first data state, and the third data state corresponds to a threshold voltage state lower than the second data state.

7. The nonvolatile memory device as set forth in claim 5, wherein

the memory cell array includes a flag memory cell for storing program execution information,

the program execution information is updated whenever programming for each data state is completed.

8. The nonvolatile memory device as set forth in claim 7, wherein if a program fail is generated from one of plural programming stages respective to the data states, the control unit detects the stage from which the program fail is generated by referring to the program execution information stored in the flag memory cell.

9. The nonvolatile memory device as set forth in claim 5, further comprising:

an error correction circuit detecting whether there is an error from data stored in the memory cell array,

wherein if a program fail is generated from one of plural programming stages respective to the data states, the control unit detects the stage from which the program fail is generated by referring to whether an error of read data is correctable by the error correction circuit.

10. The nonvolatile memory device as set forth in claim 5, further comprising:

a memory controller comprising a flag register for storing program execution information,

wherein the program execution information is updated whenever the programming for each data state is completed.

11. The nonvolatile memory device as set forth in claim 10, wherein if a program fail is generated from one of plural programming stages respective to the data states, the control unit detects the stage from which the program fail is generated by referring to the program execution information stored in the flag register.

12. The nonvolatile memory device as set forth in claim 11, wherein the control unit determines a read voltage for reading the LSB data based on a detection result of the program fail stage.

13. The nonvolatile memory device as set forth in claim 12, wherein if the program fail is generated while programming the first and second data states, the control unit determines a voltage between an erasure state and the first data state as the read voltage.

14. The nonvolatile memory device as set forth in claim 12, wherein if the program fail is generated while programming the third data state, the control unit determines a voltage between the second and third data states as the read voltage.

15. The nonvolatile memory device as set forth in claim 2, wherein the second multi-bit programming method programs the LSB and MSB data to make each threshold voltage correspond with one data state.

16. A nonvolatile memory device comprising:

a flash memory device including a memory cell array including a plurality of multi-level cells; and

a memory controller configured to control the flash memory device to program the multi-level cells by one of plural multi-bit programming methods with reference to a characteristic of data to be stored,

wherein at least one of the plural multi-bit programming methods maintains least significant bit (LSB) data when there is a program fail with most significant bit (MSB) data.

17. The nonvolatile memory device as set forth in claim 16, wherein

the plural multi-bit programming methods include first and second multi-bit programming methods,

the memory controller is configured to control the flash memory device to conduct a programming operation by the first multi-bit programming method if the data to be stored is unnecessary to have high reliability and to conduct a programming operation by the second multi-bit programming method if the data to be stored requires high reliability.

18. The nonvolatile memory device as set forth in claim 17, wherein in programming the MSB data by the second multi-bit programming method, the programming is carried out for another data state after programming for a data state.

19. The nonvolatile memory device as set forth in claim 17, wherein the second multi-bit programming method programs the LSB and MSB data to make each threshold voltage correspond with one data state.

20. A programming method of a nonvolatile memory device, comprising:

selecting one of a plurality of multi-bit programming methods with reference to a characteristic of data to be stored; and

storing data in a memory cell array using the selected multi-bit programming method, at least one of the plurality of multi-bit programming methods maintaining least significant bit (LSB) data when there is a program fail of most significant bit (MSB) data,

wherein the plural multi-bit programming methods include first and second multi-bit programming methods, the first multi-bit programming method is selected if an address of the data to be stored is correspondent with a first area of the memory cell array and the second multi-bit programming method is selected if the address of the data to be stored is correspondent with a second area of the memory cell array.

21-128. -128. (canceled)