ADAPTIVE EQUALIZER CIRCUIT

• US 20090310666A1
• Filed: 08/18/2009
• Published: 12/17/2009
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Masaki, Shunichiro, Gotoh, Kohtaroh, YAMAGUCHI, Hisakatsu, Ishida, Hideki
• Granted Patent: US 8,270,462 B2
• Time in Patent Office: Days
• US Class Current: 375/232
• CPC Class Codes: H04B 3/145 variable equalisers
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½ unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.

Claims

1. An adaptive equalizer circuit, comprising:

an equalizer circuit configured to produce an output data signal by correcting an input data signal waveform for each unit time in response to an equalizing factor;

a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing indicated by a clock signal synchronized with the output data;

a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½

unit time away from the predetermined timing indicated by the clock signal; and

a control unit configured to detect, multiple times, a predetermined data pattern having consecutive data items of a first logic value followed by a data item of a second logic value, and to adjust the equalizing factor such that a value of a detection result obtained by the data detecting circuit and a value of a detection result obtained by the boundary detecting circuit for the data item of the second logic value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.

2. The adaptive equalizer circuit as claimed in claim 1, wherein the control circuit includes a detection circuit configured to detect the predetermined data pattern by detecting a match with a pattern defining a detection target, and a number of consecutive data items of the first logic value is variable in the pattern defining the detection target.

3. The adaptive equalizer circuit as claimed in claim 1, wherein the control circuit is configured to assign a first value to a case of the values of the detection results being equal to each other, to assign a second value responsive to the first value to a case of the values of the detection results being different from each other, to obtain an accumulated sum of the first value and the second value for the multiple-time detections, and to adjust the equalizing factor in response to the accumulated sum.

4. The adaptive equalizer circuit as claimed in claim 3, wherein the control circuit is configured to repeatedly obtain the accumulated sum, to repeatedly adjust the equalizing factor in response to an absolute value of the accumulated sum, and to allow a direction of change of the equalizing factor to be set when the absolute value consecutively assumes the same value.

5. The adaptive equalizer circuit as claimed in claim 1, wherein the control circuit is configured to adjust the equalizing factor each time the predetermined data pattern is detected a predetermined number of times, and to allow the predetermined number to be variably set.

6. The adaptive equalizer circuit as claimed in claim 1, further comprising a clock recovery circuit configured to generate the clock signal in response to a detection result obtained by the data detecting circuit and a detection result obtained by the boundary detecting circuit.

7. The adaptive equalizer circuit as claimed in claim 1, wherein the boundary detecting circuit is configured to generate a first detection result by detecting a signal level of the output data signal at a timing that is +½

unit time away from the predetermined timing indicated by the clock signal, to generate a second detection result by detecting a signal level of the output data signal at a timing that is −

½

unit time away from the predetermined timing indicated by the clock signal, and to supply the first detection result and the second detection result to the control circuit as detection results.

8. The adaptive equalizer circuit as claimed in claim 1, wherein the control circuit is configured to adjust the equalizing factor such that a value of a detection result obtained by the data detecting circuit and a value of the first detection result obtained by the boundary detecting circuit for the data item of the second logic value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times, and such that the value of the detection result obtained by the data detecting circuit and a value of the second detection result obtained by the boundary detecting circuit for the data item of the second logic value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.

9. The adaptive equalizer circuit as claimed in claim 7, wherein the control circuit is configured to allow either one of the first detection result and the second detection result to be selected for use in the adjustment of the equalizing factor.

10. The adaptive equalizer circuit as claimed in claim 1, wherein the equalizing factor is a coefficient configured to control a gain of the equalizer circuit.