Performing Die-to-Wafer Stacking by Filling Gaps Between Dies
First Claim
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1. A method of forming an integrated circuit structure, the method comprising:
- providing a bottom wafer comprising a plurality of bottom semiconductor chips;
providing a plurality of top dies, each bonded to one of the plurality of bottom semiconductor chips;
forming an enclosure ring on, and close to an outer parameter of, the bottom wafer;
applying a protecting material filling spacings between the plurality of top dies, wherein a top surface of the protecting material, top surfaces of the top dies, and a top surface of the enclosure ring are leveled;
forming a planar dielectric layer on the plurality of top dies and the protecting material; and
forming a conductive feature in the planar dielectric layer, wherein the conductive feature is electrically connected to at least one of the plurality of top dies and the plurality of bottom semiconductor chips.
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Abstract
An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.
25 Citations
18 Claims
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1. A method of forming an integrated circuit structure, the method comprising:
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providing a bottom wafer comprising a plurality of bottom semiconductor chips; providing a plurality of top dies, each bonded to one of the plurality of bottom semiconductor chips; forming an enclosure ring on, and close to an outer parameter of, the bottom wafer; applying a protecting material filling spacings between the plurality of top dies, wherein a top surface of the protecting material, top surfaces of the top dies, and a top surface of the enclosure ring are leveled; forming a planar dielectric layer on the plurality of top dies and the protecting material; and forming a conductive feature in the planar dielectric layer, wherein the conductive feature is electrically connected to at least one of the plurality of top dies and the plurality of bottom semiconductor chips. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of forming an integrated circuit structure, the method comprising:
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providing a bottom wafer comprising a plurality of bottom semiconductor chips; bonding a plurality of top dies, each onto one of the plurality of bottom semiconductor chips; forming an enclosure ring on, and close to an outer parameter of, the bottom wafer; applying a protecting material filling spacings between the plurality of top dies, wherein the protecting material is enclosed by the enclosure ring; solidifying the protecting material; polishing to planarize the protecting material, the plurality of top dies, and the enclosure ring; forming a planar dielectric layer on the plurality of top dies, the protecting material, and the enclosure ring; and forming a copper line in the planar dielectric layer, wherein the copper line is electrically connected to at least one of the plurality of top dies and the plurality of bottom semiconductor chips. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification