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Performing Die-to-Wafer Stacking by Filling Gaps Between Dies

  • US 20090311829A1
  • Filed: 06/17/2008
  • Published: 12/17/2009
  • Est. Priority Date: 06/17/2008
  • Status: Active Grant
First Claim
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1. A method of forming an integrated circuit structure, the method comprising:

  • providing a bottom wafer comprising a plurality of bottom semiconductor chips;

    providing a plurality of top dies, each bonded to one of the plurality of bottom semiconductor chips;

    forming an enclosure ring on, and close to an outer parameter of, the bottom wafer;

    applying a protecting material filling spacings between the plurality of top dies, wherein a top surface of the protecting material, top surfaces of the top dies, and a top surface of the enclosure ring are leveled;

    forming a planar dielectric layer on the plurality of top dies and the protecting material; and

    forming a conductive feature in the planar dielectric layer, wherein the conductive feature is electrically connected to at least one of the plurality of top dies and the plurality of bottom semiconductor chips.

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