Integrated Circuit Using Complementary Junction Field Effect Transistor and MOS Transistor in Silicon and Silicon Alloys

• US 20090311837A1
• Filed: 06/26/2009
• Published: 12/17/2009
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Kapoor, Ashok K.
• Granted Patent: US 7,915,107 B2
• Time in Patent Office: Days
• US Class Current: 438/186
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 27/0611 integrated circuits having a two-dimensional layout of components without a common active region
• CPC Class Codes: H01L 27/098 the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Claims

1. A method for fabricating a junction field effect transistor, the method comprising:

forming a first impurity region of a first conductivity type in a semiconductor substrate;

forming a second impurity region of a first conductivity type in the semiconductor substrate;

forming a channel region of the first conductivity type between the first and second impurity regions, wherein the channel region has a maximum length of less than 100 nm;

forming a gate electrode region of a second conductivity type such that the gate electrode region overlays the semiconductor substrate;

diffusing impurities of the second conductivity type from the gate electrode region into the semiconductor substrate to form a gate region that is substantially aligned with the gate electrode region.

2. The method of claim 1, further comprising:

forming a source electrode region of the first conductivity type which overlays the semiconductor substrate;

wherein forming the first impurity region comprises diffusing impurities of the first conductivity type from the source electrode region into the semiconductor substrate.

3. The method of claim 1, further comprising:

forming a drain electrode region of the first conductivity type which overlays the semiconductor substrate;

wherein forming the second impurity region comprises diffusing impurities of the first conductivity type from the drain electrode region into the semiconductor substrate.

4. The method of claim 1, wherein:

the first impurity region comprises a source region; and

the second impurity region comprises a drain region.

5. The method of claim 1, further comprising:

forming a well region of the second conductivity type in the semiconductor substrate of the first conductivity type;

wherein;

forming the first impurity region comprises forming the first impurity region in the well region;

forming the second impurity region comprises forming the second impurity region in the well region;

forming the channel region comprises forming the channel region in the well region; and

diffusing impurities comprises diffusing impurities of the second conductivity type from the gate electrode region into the well region to form the gate region.

6. The method of claim 5, wherein the well region comprises a floating well region.

7. The method of claim 5, further comprising forming an insulator region in the semiconductor substrate such that it surrounds at least a portion of the well region.

8. The method of claim 1, further comprising forming a gate contact region on the gate electrode region such that it is in ohmic contact with the gate region.

9. The method of claim 8, wherein the gate contact region is substantially aligned with the gate electrode region.

10. The method of claim 1, wherein the channel region is substantially aligned with the gate region.

11. The method of claim 1, further comprising:

forming a first link region of the first conductivity type in the semiconductor substrate, the first link region connecting the first impurity region and the channel region; and

forming a second link region of the first conductivity type in the semiconductor substrate, the second link region connecting the second impurity region and the channel region.

12. The method of claim 1, wherein:

the first conductivity type comprises n-type; and

the second conductivity type comprises p-type.

13. The method of claim 1, wherein:

the first conductivity type comprises p-type; and

the second conductivity type comprises n-type.

14. The method of claim 1, wherein the channel region has a maximum length of less than 70 nm.

15. A method for fabricating one or more semiconductor devices comprising the steps of:

building one or more isolation regions in a semiconductor substrate of a first conductivity type, the isolation regions being filled with dielectric material;

doping one or more regions in the semiconductor substrate to form one or more well regions of the first conductivity type and one or more well regions of the second conductivity type opposite to the first conductivity type;

forming one or more channel regions in the one or more well regions wherein each channel region is of a conductivity type opposite to the conductivity type of the corresponding well region;

depositing a first semiconductor layer on the semiconductor substrate;

doping the first semiconductor layer selectively above each well region to dope one or more drain contact regions, one or more source contact regions, one or more gate electrode regions, and one or more well contact regions;

wherein each drain and source regions are doped with a conductivity type opposite to the conductivity type of the corresponding well region;

wherein each gate electrode and well contact regions are doped with the conductivity type of the corresponding well region;

depositing a first dielectric layer on top of the first semiconductor layer to form a blocking layer;

masking and etching the first semiconductor layer for forming one or more drain contact regions, one or more source contact regions, one or more gate electrode regions, and one or more well contact regions;

forming one or more first source link regions and one or more first drain link regions in the one or more well regions by ion implantation;

wherein each first source link region connects between a region immediately underneath a source contact region and a channel region;

wherein each first drain link region connects between a region immediately underneath a drain contact region and a channel region; and

wherein each first source link region and each first drain link region are implanted with a conductivity type opposite to the conductivity type of the corresponding well region;

annealing the semiconductor substrate with the first semiconductor layers and the first dielectric layer;

filling up the regions etched away in the first semiconductor layer during the masking and etching step with dielectric material for forming a planar surface;

removing the blocking layer non-selectively;

forming silicide on top of the first semiconductor layer selectively;

depositing a second dielectric layer on the semiconductor substrate and etching to form contact holes; and

depositing and etching one or more metal layers on the semiconductor substrate for forming interconnections.

16. The method as in claim 15, wherein the annealing step comprises:

forming a gate region underneath each gate electrode region wherein the gate region has an impurity concentration doped from the gate electrode region;

forming a second source region underneath each source contact region wherein the second source region has an impurity concentration doped from the source contact region;

wherein the second source region connects with a first source region; and

forming a second drain region underneath each drain contact region wherein the second drain region has an impurity concentration doped from the drain contact region;

wherein the second drain region connects with a first drain region.

17. The method as in claim 16, wherein:

the semiconductor substrate is made of silicon;

the first semiconductor layer is made of polycrystalline silicon; and

the first dielectric layer is made of silicon nitride.

18. The method as in claim 15, further comprising, after the step of forming one or more channel regions, the steps of:

forming a gate dielectric layer on top of the semiconductor substrate and selectively removing the gate dielectric layer over a source region, a drain region, and a well region for forming an MOS transistor; and

selectively removing the gate dielectric layer over a channel region, a source region, a drain region, and a well region for forming a junction field effect transistor.

19. A method for fabricating a junction field effect transistor, the method comprising:

forming a first impurity region of a first conductivity type in a semiconductor substrate;

forming a second impurity region of a first conductivity type in the semiconductor substrate;

forming a channel region of the first conductivity type between the first and second impurity regions, wherein the channel region has a maximum length of less than 100 nm;

forming a gate electrode region of a second conductivity type; and

forming a gate region that is substantially aligned with the gate electrode region.

20. The method of claim 19, wherein the channel region has a maximum length of less than 70 nm.