One Transistor Memory Cell with Bias Gate

• US 20090311845A1
• Filed: 08/07/2009
• Published: 12/17/2009
• Est. Priority Date: 09/07/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Doyle, Daniel H., Haller, Gordon
• Granted Patent: US 7,944,743 B2
• Time in Patent Office: Days
• US Class Current: 438/404
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

Claims

1-21. -21. (canceled)

22. A method for making a semiconductor memory device, the method comprising:

providing a semiconductor substrate;

forming shallow-trench-isolations in the semiconductor substrate;

forming floating bodies and a base substrate out of the semiconductor substrate by removing portions of the semiconductor substrate and the shallow-trench-isolations, the floating bodies each being a disconnected portion of the semiconductor substrate held separate from the base substrate by the shallow-trench-isolations;

forming a conductive layer between the floating bodies and the base substrate; and

forming MOS transistors each including one of the floating bodies,

wherein the floating body of each of the MOS transistors is adapted to store a data bit during operation of the memory device.

23. The method of claim 22, further comprising forming a nitride cap on a surface of the semiconductor substrate between the shallow-trench-isolations before forming the floating bodies, the nitride cap further holding the floating bodies separate from the base substrate.

24. The method of claim 22, wherein the semiconductor substrate comprises a single crystalline silicon.

25. The method of claim 24, wherein the conductive layer is a polysilicon layer.

26. The method of claim 25, wherein forming the conductive layer comprises depositing polysilicon into gaps formed between the floating bodies such that the conductive layer is self-aligned to the floating bodies.

27-40. -40. (canceled)