METHOD OF FABRICATING A GATE STRUCTURE

• US 20090311855A1
• Filed: 08/20/2009
• Published: 12/17/2009
• Est. Priority Date: 10/19/2007
• Status: Abandoned Application

• Current Assignee: Amanda L. Tessier, Brian L. Tessier, Chienfan Yu, Daewon Yang, Denise Pendleton-Lipinski, Richard A. Bruff, Richard A. Conti, Yun-Yu Wang
• Original Assignee: Amanda L. Tessier, Brian L. Tessier, Chienfan Yu, Daewon Yang, Denise Pendleton-Lipinski, Richard A. Bruff, Richard A. Conti, Yun-Yu Wang
• Inventors: Wang, Yun-Yu, Tessier, Brian L., Tessier, Amanda L., Conti, Richard A., Yang, Daewon, Pendleton-Lipinski, Denise, Bruff, Richard A., Yu, Chienfan
• Application Number:
  US12/544,425
• Publication Number:
  US 20090311855A1
• Time in Patent Office: Days
• US Class Current: 438/587
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

Claims

1. A method of fabricating a gate structure, the method comprising:

forming a plurality of gates on a substrate; and

depositing at least one dual-layer liner to fill a vertical space between adjacent gates, the at least one dual-layer liner including an intrinsically stressed protective layer and an intrinsically stressed filling layer, the intrinsic stress of each of the intrinsically stressed protective layer and the intrinsically stressed filling layer being variable,

wherein the depositing is a single step deposition of high density plasma (HDP) film.

2. The method of claim 1, wherein the depositing of the protective layer is at a maximum power of approximately 300 W;

and the depositing of the filling layer is at a power ranging from approximately 1000 W to approximately 2000 W.

3. The method of claim 1, further comprising depositing a capping layer on the at least one dual-layer liner.

4. The method of claim 3, wherein the depositing of the protective layer is at a maximum power of approximately 300 W;

the depositing of the filling layer is at a power ranging from approximately 1000 W to approximately 2000 W; and

the depositing of the capping layer is at a power ranging from approximately 300 W to approximately 1500 W.

5. The method of claim 3, further comprising depositing a base layer before depositing the at least one dual-layer liner.

6. The method of claim 5, wherein the depositing of the base layer is at a power ranging from approximately 300 W to approximately 1500 W, the depositing of the protective layer is at a maximum power of approximately 300 W;

the depositing of the filling layer is at a power ranging from approximately 1000 W to approximately 2000 W; and

the depositing of the capping layer is at a power ranging from approximately 300 W to approximately 1500 W.

7. The method of claim 1, further comprising depositing a base layer before depositing the at least one dual-layer liner.

8. The method of claim 7, wherein the depositing of the base layer is at a power ranging from approximately 300 W to approximately 1500 W, the depositing of the protective layer is at a maximum power of approximately 300 W;

and the depositing of the filling layer is at a power ranging from approximately 1000 W to approximately 2000 W.