SHARED MEMORY BURST COMMUNICATIONS

• US 20090313440A1
• Filed: 12/16/2008
• Published: 12/17/2009
• Est. Priority Date: 06/11/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Kyoung Heon, Park, Young Eun, Oh, Im Bum, Jo, Chul Min, Kim, Young Lak, Lee, Sang Hyun
• Granted Patent: US 8,230,180 B2
• Time in Patent Office: Days
• US Class Current: 711/149
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A method and apparatus are provided for sharing multipath-accessible memory between a plurality of processors, the method including connecting the plurality of processors in read/write communication to a same shared memory region; connecting the plurality of processors in read communication to a same semaphore area; selectably connecting one of the plurality of processors in write communication to the same semaphore area; exchanging shared memory access command messages between two processors for negotiating access to the same shared memory region; and storing protected variables indicative of the currently negotiated access to the same shared memory region in the same semaphore area, wherein the shared memory region has a channel relative to each processor, each channel having at least one buffer disposed for transferring a plurality of data packets in a burst mode.

Claims

1. A multipath-accessible memory device comprising:

a plurality of input/output ports, each disposed for connection to one of a plurality of processors;

a shared memory region connected in read/write communication to each of the plurality of ports;

a plurality of mailboxes, each connected in read communication to one of the plurality of ports for receiving shared memory access command messages from other processors;

a semaphore area connected in read communication to each of the plurality of ports and connected in selectable write communication to one of the plurality of ports for storing protected variables indicative of the currently negotiated access to the shared memory region,

wherein the shared memory region has at least one channel relative to each processor, the at least one channel having at least one buffer disposed for transferring a plurality of data packets in a burst mode.

2. The device of claim 1, the at least one channel comprising a transmit channel and a receive channel relative to each processor.

3. The device of claim 1 wherein the number of the plurality of processors is two, the number of the plurality of input/output ports is two, and the number of the plurality of mailboxes is two.

4. The device of claim 3 wherein;

a first port of the two ports is connected to a first processor of the two processors;

a second port of the two ports is connected to a second processor of the two processors;

the shared memory region is configured to be accessed selectively by the first processor or the second processor, and configured to store a plurality of data packets; and

the mailbox is configured to store command and data information for a plurality of data packets.

5. The device of claim 1 wherein the shared memory region has a plurality of channels, and at least one of the channels stores a plurality of data packets.

6. The device of claim 5 wherein the at least one of the channels has a plurality of buffers, and at least one of the buffers stores a data packet.

7. The device of claim 2 wherein the size of the transmit channel is different than the size of the receive channel.

8. The device of claim 1, each of the plurality of mailboxes comprising:

a command field;

a channel index field; and

a packet count field.

9. The device of claim 1, each of the plurality of mailboxes comprising an interrupt generator for interrupting a respective processor when its mailbox has been updated.

10. The device of claim 1 wherein the at least one buffer has a first field indicating the actual amount of data in that buffer.

11. The device of claim 1, further comprising at least one unshared memory region connected in read/write communication to one of the plurality of ports.

12. The device of claim 1 wherein the shared memory region is configured by a plurality of DRAM memory cells disposed in matrix of rows and columns.

13. A method of sharing multipath-accessible memory between a plurality of processors, the method comprising:

connecting the plurality of processors in read/write communication to a same shared memory region;

connecting the plurality of processors in read communication to a same semaphore area;

selectably connecting one of the plurality of processors in write communication to the same semaphore area;

exchanging shared memory access command messages between two processors for negotiating access to the same shared memory region; and

storing protected variables indicative of the currently negotiated access to the same shared memory region in the same semaphore area,

wherein the shared memory region has a channel relative to each processor, each channel having at least one buffer disposed for transferring a plurality of data packets in a burst mode.

14. The method of claim 13, the channel relative to at least one of the plurality of processors comprising a transmit channel and a receive channel.

15. The method of claim 13, further comprising:

connecting each of the plurality of processors in write communication with at least one outgoing mailbox for that processor; and

connecting each of the plurality of processors in read communication with at least one incoming mailbox for that processor.

16. The method of claim 13 wherein the outgoing mailbox for one of the plurality of processors is the incoming mailbox for another of the plurality of processors.

17. The method of claim 13 wherein the number of the plurality of processors is two.

18. The method of claim 13, further comprising:

a first processor acquiring ownership of the shared memory region;

the first processor writing at least one data packet to the shared memory region;

the first processor writing a data transfer command and data transfer information to the mailbox of a second processor;

the second processor reading the data transfer command and data transfer information from its mailbox; and

the second processor reading the at least one data packet from the shared memory region.

19. A mobile communications device comprising:

a plurality of processors;

a plurality of input/output ports, each disposed for connection to one of the plurality of processors;

a shared memory region connected in read/write communication to each of the plurality of ports;

a plurality of mailboxes, each connected in read communication to one of the plurality of ports for receiving shared memory access command messages from other processors;

a semaphore area connected in read communication to each of the plurality of ports and connected in selectable write communication to one of the plurality of ports for storing protected variables indicative of the currently negotiated access to the shared memory region,

wherein the shared memory region has at least one channel relative to each processor, the at least one channel having at least one buffer disposed for transferring a plurality of data packets in a burst mode.

20. A mobile communications apparatus comprising:

a first processor;

at least one second processor; and

a multipath-accessible memory configured to transfer a plurality of data packets between the first and at least one second processors;

wherein the multipath-accessible memory is configured to be selectively accessed by the first or at least one second processors and to store command and data transit information for transferring the plurality of data packets between the processors.

21. The apparatus of claim 20, each processor comprising:

an inter-processor communications driver; and

a device driver connected in signal communication with the inter-processor communications driver.

22. The apparatus of claim 21 wherein each device driver supports an application programming interface (API), each API configured to read or write command information and to read or write a plurality of data packets in accordance with the command information.

23. The apparatus of claim 22 wherein the command information is written to the mailbox associated with the port of the other processor.

24. The apparatus of claim 20, the multipath-accessible memory comprising:

a plurality of input/output ports, each disposed for connection to one of the processors;

a shared memory region connected in read/write communication to each of the plurality of ports;

a plurality of mailboxes, each connected in read communication to one of the plurality of ports for receiving shared memory access command messages from other processors;

a semaphore area connected in read communication to each of the plurality of ports and connected in selectable write communication to one of the plurality of ports for storing protected variables indicative of the currently negotiated access to the shared memory region,

wherein the shared memory region has at least one channel relative to each processor, the at least one channel having at least one buffer disposed for transmitting and receiving a plurality of data packets in a burst mode, respectively.