CIRCUIT WITH A PLURALITY OF MODES OF OPERATION

• US 20090313461A1
• Filed: 06/16/2008
• Published: 12/17/2009
• Est. Priority Date: 06/16/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: KLUG, FRANZ
• Granted Patent: US 9,087,219 B2
• Time in Patent Office: Days
• US Class Current: 712/229
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode

Abstract

A circuit capable of being operated in a first and a second mode of operation comprises a storage location adapted to store at least a first state, a second state and a third state, wherein the circuit is adapted to switch to the first mode of operation when the storage location acquires the first or the third state, and wherein the circuit is adapted to switch to the second mode of operation when the storage location acquires the second state.

Claims

1. A circuit adapted to be operated in a first and a second mode of operation, comprising:

a storage location adapted to store at least a first state, a second state and a third state,

wherein the circuit is adapted to switch to the first mode of operation when the storage location acquires the first state or the third state, and

wherein the circuit is adapted to switch to the second mode of operation when the storage location acquires the second state.

2. The circuit according to claim 1, wherein the circuit is further adapted to be operated in a third mode of operation, wherein the storage location is further adapted to store a fourth state, and wherein the circuit is further adapted to switch to the third mode of operation when the storage location acquires the fourth state.

3. The circuit according to claim 1, wherein the storage location is adapted such that values corresponding to the states are not consecutive when being arranged in an ascending order.

4. The circuit according to claim 1, wherein the circuit is adapted such that a security level or a level of resistance with respect to attacks on the circuit is higher for the first mode of operation than for the second mode of operation, or wherein the circuit is adapted such that in the first mode of operation, the circuit is halted.

5. The circuit according to claim 4, wherein the circuit is adapted to process or transfer data to an external component, wherein the data is masked by a changeable mask during processing or transferring, or wherein the data is blinded based on a changeable key, wherein the different modes of operation differ with respect to at least one of a frequency of mask changes and key changes or with respect to at least one of a mask length and a key length, wherein the circuit is adapted such that the first mode corresponds to the highest frequency or the longest key.

6. The circuit according to claim 4, wherein the circuit is a crypto processor and the circuit is adapted such that the first mode corresponds to a reset of the crypto processor or a halt mode of the crypto processor, so that a processing of data is stopped.

7. The circuit according to claim 4, wherein the circuit is a crypto processor, and the different modes of operation differ with respect to at least one of a crypto algorithm, a key length and a key change frequency.

8. The circuit according to claim 4, wherein the circuit is adapted such that the different modes of operation comprise different correlations of power consumption and processed data, and such that the first mode of operation comprises the lowest level of correlation.

9. The circuit according to claim 4, wherein the circuit is adapted such that the different modes of operation comprise different bandwidths of potential power consumptions.

10. The circuit according to claim 4, wherein the circuit comprises a true random number generator and a pseudo random number generator, wherein the circuit is adapted such that the true random number generator is used for initializing the pseudo random number generator, and wherein the circuit is adapted such that the different modes of operation correspond to different frequencies of the initialization of the pseudo random number generator.

11. The circuit according to claim 1, wherein the storage location is a register.

12. The circuit according to claim 11, wherein the register is a control register or a special function register.

13. The circuit according to claim 1, wherein the circuit is an integrated circuit.

14. The circuit according to claim 1, wherein the circuit is comprised in a processor, crypto processor or application-specific integrated circuit.

15. An integrated circuit comprising:

a register adapted to store a first number of states and a second number of states, wherein the first number is at least 3 and the second number is at least 1;

wherein the integrated circuit is adapted to switch to a selected mode of operation of a plurality of modes of operation, depending on a state stored in the register;

wherein each state of the first number of states corresponds to exactly one mode of operation of the plurality of modes of operation;

wherein a selected mode of operation is a mode of operation corresponding to the state stored in the register when the state stored in the register is one of the first number of states;

wherein the selected mode of operation is a predetermined mode of operation of the plurality of modes of operation when the state corresponds to a state of the second number of states; and

wherein the predetermined mode of operation comprises a security level or a resistance level with respect to an attack on the integrated circuit which is equal to or higher than the respective security or resistance levels of the other modes of operation of the plurality of modes of operation, or wherein the predetermined mode of operation corresponds to a mode in which the integrated circuit is at least in part halted.

16. The integrated circuit according to claim 15, wherein the integrated circuit is adapted such that the states of the first number of states correspond to values which are not consecutive when arranged in an ascending order.

17. The integrated circuit according to claim 15, wherein the register is adapted to store exactly the first number of states and the second number of states.

18. The integrated circuit according to claim 15, wherein the second number is equal to or higher than double the first number.

19. The integrated circuit according to claim 15, wherein the integrated circuit is adapted to process or transfer data to an external component, wherein the data are masked during processing or transferring by a changeable mask or blinded based on a changeable key, wherein the modes of operation differ with respect to at least one of a frequency of mask changes, key changes, a mask length and a key length, and wherein the predetermined mode of operation corresponds to the mode of operation with the highest frequency or the longest key or mask.

20. The integrated circuit according to claim 15, wherein the integrated circuit comprises a crypto processor that is adapted such that the predetermined mode of operation comprises resetting the crypto processor or halting the crypto processor, such that data processing is stopped.

21. The integrated circuit according to claim 15, wherein the integrated circuit comprises a crypto processor, and wherein the crypto processor is adapted such that the different modes of operation differ with respect to at least one of a crypto algorithm, a key length and a key change frequency.

22. An apparatus for being operated in at least a first mode and a second mode of operation, comprising:

a storing means for storing at least a first state, a second state and a third state; and

a switching means for switching the apparatus to the first mode of operation when the storage means acquires the first or the third states, and for switching the apparatus to the second mode of operation when the storing means acquires the second state.

23. A method for switching a circuit in a first mode or a second mode of operation, comprising:

determining a state of a storage location adapted to store at least a first state, a second state and a third state;

switching the circuit to the first mode of operation when the determined state is the first state or the third state; and

switching the circuit to the second mode of operation when the determined state is the second state.

24. A method for switching an integrated circuit into a selected mode of operation, comprising:

determining a state of a register adapted to store a first number of states and a second number of states, wherein the first number is at least 3 and the second number is at least 1;

switching the integrated circuit to the selected mode of operation of a plurality of modes of operation corresponding to the determined state when the determined state is a state of a first number of states;

switching the integrated circuit to a predetermined mode of operation of the plurality of modes of operation when the determined state is a state of the second number of states,

wherein the predetermined mode of operation comprises a security level or resistance level with respect to an attack on the integrated circuit which is equal to or higher than the respective security or resistance levels of the other modes of operation of the plurality of modes of operation, or wherein the predetermined mode of operation corresponds to a mode in which the integrated circuit is at least in part halted.

25. A computer program for performing, when running on a processor, a method for switching a circuit to a first mode of operation or a second mode of operation, comprising:

determining a state of a storage location adapted to store at least a first state, a second state and a third state;

switching the circuit to the first mode of operation when the determined state is the first state or the third state; and

switching the circuit to the second mode of operation when the determined state is the second state.