NOISE REDUCTION APPARATUS AND METHOD OF DYNAMIC POWER MANAGEMENT PROCESSOR

• US 20090313491A1
• Filed: 11/05/2008
• Published: 12/17/2009
• Est. Priority Date: 06/16/2008
• Status: Active Grant

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Oh, Jang-Geun
• Granted Patent: US 8,117,473 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A noise reduction apparatus and method of a processor to which a dynamic power management technique is applied. The noise reduction apparatus includes a mode setting unit for detecting a use state of a processor and setting an operation mode; and a power supply unit for supplying voltage corresponding to the operation mode set by the mode setting unit. The operation mode includes a general mode in which the processor normally operates; a sleep mode in which activity of the processor is suspended; and a low frequency mode in which the processor operates at voltage and clock frequency lower than those of the general mode and higher than those of the sleep mode. The mode setting unit changes between the general mode and the sleep mode, wherein the processor is set to the low frequency mode as an intermediate step.

Claims

1. A noise reduction apparatus of a dynamic power management processor, comprising:

a mode setting unit configured to detect a use state of a processor and to set an operation mode of the processor; and

a power supply unit configured to supply a voltage at a level corresponding to the operation mode set by the mode setting unit, wherein

the operation mode includes a general mode in which the processor normally operates;

a sleep mode in which activity of the processor is suspended; and

a low frequency mode in which the processor operates at a low frequency mode voltage and a low frequency mode clock frequency lower than a general mode voltage and a general mode clock frequency and higher than a sleep mode voltage and a sleep mode clock frequency, and

the mode setting unit is further configured to change the operating mode of the processor between the general mode and the sleep mode via the low frequency mode as an intermediate step.

2. The noise reduction apparatus as claimed in claim 1, wherein

the low frequency mode includes

a low speed mode in which the processor virtualizes a bus signal and in which the processor operates at a low speed mode clock frequency and a low speed mode bus frequency that are lower than the general mode clock frequency and a general mode bus frequency, and

an ultra low speed mode in which the processor operates at an ultra low speed mode voltage and an ultra low speed mode clock frequency lower than a low speed mode voltage and the low speed mode clock frequency, and

the mode setting unit is configured to change the operating mode of the processor between the general mode and the sleep mode via both the low speed mode and the ultra low speed mode as the intermediate step.

3. The noise reduction apparatus as claimed in claim 2,

wherein the ultra low speed mode includes controlling a phase locked loop (PLL) so that the ultra low speed mode voltage and the ultra low speed mode clock frequency of the processor are set to be lower than the low speed mode voltage and the low speed mode clock frequency.

4. The noise reduction apparatus as claimed in claim 2,

wherein the ultra low speed mode includes virtualizing the bus signal so that the ultra low speed mode voltage and the ultra low speed mode clock frequency of the processor are set to be lower than the low speed mode voltage and the low speed mode clock frequency.

5. The noise reduction apparatus as claimed in claim 1,

wherein the mode setting unit is configured to set the operation mode of the processor to the low frequency mode when the change between the general mode and the sleep mode occurs in response to a periodically generated signal.

6. A noise reduction apparatus of a dynamic power management processor, the apparatus comprising:

a mode setting unit configured to detect a use state of a processor and to set an operation mode of the processor; and

a power supply unit configured to supply a voltage corresponding to the operation mode set by the mode setting unit,

wherein the mode setting unit is configured to change the operation mode of the processor from a sleep mode to a low frequency mode in response to receiving a periodically generated signal during the sleep mode of the processor.

7. The noise reduction apparatus as claimed in claim 6, wherein the low frequency mode including a low frequency mode voltage and a low frequency mode clock frequency lower than a general mode voltage and a general mode clock frequency and higher than a sleep mode voltage and a sleep mode clock frequency.

8. The noise reduction apparatus as claimed in claim 7, wherein the low frequency mode comprises:

a low speed mode in which the processor virtualizes a bus signal and operates at a low speed mode clock frequency and a low speed mode bus frequency lower than the general mode clock frequency and a general mode bus frequency, and

an ultra low speed mode in which the processor operates at an ultra low speed mode voltage and an ultra low speed mode clock frequency lower than the low speed mode voltage and the low speed mode clock frequency.

9. The noise reduction apparatus as claimed in claim 8, wherein the ultra low speed mode includes controlling a PLL so that the ultra low speed mode voltage and the ultra low speed mode clock frequency of the processor are set to be lower than the low speed mode voltage and the low speed mode clock frequency.

10. The noise reduction apparatus as claimed in claim 8, wherein the ultra low speed mode includes virtualizing the bus signal so that the ultra low speed mode voltage and the ultra low speed mode clock frequency of the processor are set to be lower than the low speed mode voltage and the low speed mode clock frequency.

11. A noise reduction method of a dynamic power management processor, comprising the steps of:

(a) detecting a use state of a processor and setting an operation mode of the processor; and

(b) supplying a voltage and a clock frequency corresponding to the set operation mode,

wherein the operation mode includes a general mode in which the processor normally operates;

a sleep mode in which activity of the processor is suspended; and

a low frequency mode in which the processor operates at a low frequency mode voltage and a low frequency mode clock frequency that are lower than a general mode voltage and a general mode clock frequency and higher than a sleep mode voltage and a sleep mode clock frequency; and

changing between the general mode and the sleep mode, including setting the operation mode of the processor to the low frequency mode as an intermediate step.

12. The noise reduction method as claimed in claim 11, wherein

the low frequency mode includes

a low speed mode in which the processor virtualizes a bus signal and operates at a low speed mode clock frequency and a low speed mode bus frequency lower than the general mode clock frequency and the general mode bus frequency, and

an ultra low speed mode in which the processor operates at an ultra low speed mode voltage and an ultra low speed mode clock frequency lower than the low speed mode voltage and the low speed mode clock frequency;

and

the step of changing between the general mode and the sleep mode includes a step of sequentially setting the operation mode of the processor to the low speed mode and then the ultra low speed mode as the intermediate step.

13. The noise reduction method as claimed in claim 12, wherein the ultra low speed mode includes controlling a PLL so that the ultra low speed mode voltage and the ultra low speed mode clock frequency are set to be lower than the low speed mode voltage and the low speed mode clock frequency.

14. The noise reduction method as claimed in claim 12, wherein the ultra low speed includes virtualizing the bus signal so that the ultra low speed mode voltage and the ultra low speed mode clock frequency of the processor are set to be lower than the low speed mode voltage and the low speed mode clock frequency.

15. The noise reduction method as claimed in claim 11, further comprising:

setting the operation mode of the processor to the low frequency mode when the step of changing between the general mode and the sleep mode occurs in response to a periodically generated signal.

16. A noise reduction method of a dynamic power management processor, comprising the steps of:

(A) detecting a use state of a processor and setting an operation mode of the processor;

(B) setting the operation mode of the processor to a sleep mode in response to the detected use state of the processor; and

(C) changing the operation mode of the processor from the sleep mode to a low frequency mode in response to receiving a periodically generated signal during the sleep mode of the processor.

17. The noise reduction method as claimed in claim 16, wherein the low frequency mode is a mode having at a low frequency mode voltage and a low frequency mode clock frequency lower than a general mode voltage and a general mode clock frequency and higher than a sleep mode voltage and a sleep mode clock frequency.

18. The noise reduction method as claimed in claim 17, wherein the low frequency mode comprises:

a low speed mode in which the processor virtualizes a bus signal and including a low speed mode clock frequency and a low speed mode bus frequency lower than the general mode clock frequency and the general mode bus frequency, and

an ultra low speed mode in which the processor operates at an ultra low speed mode voltage and an ultra low speed mode clock frequency lower than the low speed mode voltage and the low speed mode clock frequency.

19. The noise reduction method as claimed in claim 18, wherein the ultra low speed mode includes controlling a PLL so that the ultra low speed mode voltage and the ultra low speed mode clock frequency of the processor are set to be lower than the low speed mode voltage and the low speed mode clock frequency.

20. The noise reduction method as claimed in claim 18, wherein the ultra low speed mode includes virtualizing the bus signal so that the ultra low speed mode voltage and the ultra low speed mode clock frequency of the processor are set to be lower than the low speed mode voltage and the low speed mode clock frequency.