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NOISE REDUCTION APPARATUS AND METHOD OF DYNAMIC POWER MANAGEMENT PROCESSOR

  • US 20090313491A1
  • Filed: 11/05/2008
  • Published: 12/17/2009
  • Est. Priority Date: 06/16/2008
  • Status: Active Grant
First Claim
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1. A noise reduction apparatus of a dynamic power management processor, comprising:

  • a mode setting unit configured to detect a use state of a processor and to set an operation mode of the processor; and

    a power supply unit configured to supply a voltage at a level corresponding to the operation mode set by the mode setting unit, whereinthe operation mode includes a general mode in which the processor normally operates;

    a sleep mode in which activity of the processor is suspended; and

    a low frequency mode in which the processor operates at a low frequency mode voltage and a low frequency mode clock frequency lower than a general mode voltage and a general mode clock frequency and higher than a sleep mode voltage and a sleep mode clock frequency, andthe mode setting unit is further configured to change the operating mode of the processor between the general mode and the sleep mode via the low frequency mode as an intermediate step.

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