SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20090314527A1
• Filed: 06/17/2009
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SAKAKURA, Masayuki, HATANO, Kaoru, CHIDA, Akihiro, NAGATA, Takaaki
• Granted Patent: US 8,555,497 B2
• Time in Patent Office: Days
• US Class Current: 174/255
• CPC Class Codes: G06K 19/07745 Mounting details of integrated circuit chips
• CPC Class Codes: G06K 19/07747 at least one of the integrated circuit chips being mounted as a module
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0366 reinforced, e.g. by fibres, fabrics H05K1/036 takes precedence
• CPC Class Codes: H05K 2203/1163 Chemical reaction, e.g. heating solder by exothermic reaction oxidising metal H05K2203/0315
• CPC Class Codes: H05K 3/002 by liquid chemical etching
• CPC Class Codes: H05K 3/4069 : for via connections in organic insulating substrates
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor

Abstract

To form a conductive region in a prepreg without opening a through hole in a fibrous body. A wiring substrate is provided, including: an organic resin layer and a fibrous body, wherein the fibrous body is impregnated with the organic resin layer; and a wiring with which the fibrous body is impregnated and which is formed by dissolving the organic resin layer. The wiring is exposed on both surfaces of the organic resin layer and penetrates the fibrous body so that the fibrous body is positioned in the through wiring. Further, a semiconductor device is provided by adhering an integrated circuit chip having a bump to the wiring substrate so that the bump is in contact with the wiring.

Claims

1. A wiring substrate comprising:

an organic resin layer and a fibrous body, the fibrous body being impregnated with the organic resin layer, and

a wiring penetrating a portion of the fibrous body and portions of upper and lower surfaces of the organic resin layer, the portion of the fibrous body being impregnated with the wiring,

wherein the portion of the fibrous body is positioned in the wiring.

2. The wiring substrate according to claim 1,

wherein the wring includes a metal particle, and

wherein the metal particle is selected from the group consisting of copper, silver, nickel, gold, platinum, palladium, tantalum, molybdenum, titanium, and tin.

3. The wiring substrate according to claim 1, wherein the fibrous body comprises glass fiber.

4. The wiring substrate according to claim 3,

wherein the wring includes metal particles, and

wherein the metal particles include at least one element selected from the group consisting of copper, silver, nickel, gold, platinum, palladium, tantalum, molybdenum, titanium, and tin.

5. A semiconductor device comprising:

an integrated circuit chip having a first wiring;

an organic resin layer and a fibrous body, the fibrous body being impregnated with the organic resin layer, and

a second wiring penetrating a portion of the fibrous body and portions of upper and lower surfaces of the organic resin layer, the portion of the fibrous body being impregnated with the second wiring,

wherein the first wiring is in contact with the second wiring.

6. The semiconductor device according to claim 5,

wherein the second wiring includes metal particles, and

wherein the metal particles include at least one element selected from the group consisting of copper, silver, nickel, gold, platinum, palladium, tantalum, molybdenum, titanium, and tin.

7. The semiconductor device according to claim 5, wherein the fibrous body comprises glass fiber.

8. The semiconductor device according to claim 7,

wherein the second wiring includes a metal particle, and

wherein the metal particle includes an element selected from the group consisting of copper, silver, nickel, gold, platinum, palladium, tantalum, molybdenum, titanium, and tin.

9. A manufacturing method of a wiring substrate, comprising the steps of:

impregnating a fibrous body with an organic resin layer; and

forming a wiring by provision of a conductive resin including metal particles over a portion of the organic resin layer, dissolution of the organic resin layer by the conductive resin, and penetration of the metal particles through the fibrous body.

10. The manufacturing method of a wiring substrate according to claim 9,

wherein the metal particle includes at least one element selected from the group consisting of copper, silver, nickel, gold, platinum, palladium, tantalum, molybdenum, titanium, and tin.

11. The manufacturing method of a wiring substrate according to claim 9, wherein the fibrous body comprises glass fiber.

12. The manufacturing method of a wiring substrate according to claim 11,

wherein the metal particles include at least one element selected from the group consisting of copper, silver, nickel, gold, platinum, palladium, tantalum, molybdenum, titanium, and tin.

13. A manufacturing method of a semiconductor device, comprising the steps of:

forming an integrated circuit chip having a first wiring;

impregnating a fibrous body with an organic resin layer;

adhering the integrated circuit chip to the organic resin layer and the fibrous body; and

forming a second wiring which is in contact with the first wiring by provision of a conductive resin including metal particles over a portion of the organic resin layer, dissolution of the organic resin layer by the conductive resin, and penetration of the metal particles through the fibrous body.

14. The manufacturing method of a semiconductor device according to claim 13, wherein the metal particles include at least one element selected from the group consisting of copper, silver, nickel, gold, platinum, palladium, tantalum, molybdenum, titanium, and tin.

15. The manufacturing method of a semiconductor device according to claim 13, wherein the fibrous body comprises glass fiber.

16. The manufacturing method of a semiconductor device according to claim 15, wherein the metal particles include at least one element selected from the group consisting of copper, silver, nickel, gold, platinum, palladium, tantalum, molybdenum, titanium, and tin.