SEMICONDUCTOR DEVICES INCLUDING SCHOTTKY DIODES HAVING DOPED REGIONS ARRANGED AS ISLANDS AND METHODS OF FABRICATING SAME

• US 20090315036A1
• Filed: 06/26/2009
• Published: 12/24/2009
• Est. Priority Date: 08/01/2006
• Status: Active Grant

• Current Assignee: Anant Agarwal, Qingchun Zhang, Sei-Hyung Ryu
• Original Assignee: Anant Agarwal, Qingchun Zhang, Sei-Hyung Ryu
• Inventors: Agarwal, Anant, Zhang, Qingchun, Ryu, Sei-Hyung
• Granted Patent: US 8,330,244 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.

Claims

1. A semiconductor device, comprising:

a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined;

a plurality of spaced apart first doped regions arranged within the active region, the plurality of first doped regions having a second conductivity type that is opposite the first conductivity type, having a first dopant concentration, and defining a plurality of exposed portions of the semiconductor layer within the active region, wherein the plurality of first doped regions are arranged as islands in the semiconductor layer; and

a second doped region in the semiconductor layer, the second doped region having the second conductivity type and having a second dopant concentration that is greater than the first dopant concentration.

2. The semiconductor device of claim 1, wherein the islands comprise circular islands.

3. The semiconductor device of claim 1, wherein the islands have irregular shapes.

4. The semiconductor device of claim 1, wherein the islands have rectangular shapes.

5. The semiconductor device of claim 1, wherein the islands have polygonal shapes.

6. The semiconductor device of claim 1, wherein the metal layer comprises a first metal region in contact with the exposed portions of the semiconductor layer and the first doped region and a second metal region in contact with the second doped region, wherein the first metal region comprises a metal different from the second metal region.

7. The semiconductor device of claim 6, wherein the semiconductor layer comprises a silicon carbide semiconductor layer

8. The semiconductor device of claim 7, wherein the first doped region comprises p-type silicon carbide having a dopant concentration of from about 1×

10¹⁷ to about 1×

10¹⁸ cm<sup>−

3</sup>, and the second doped region comprises p-type silicon carbide having a dopant concentration of greater than about 5×

10¹⁸ cm<sup>−

3</sup>.

9. The semiconductor device of claim 1, wherein the semiconductor layer comprises an epitaxial layer of silicon carbide.

10. The semiconductor device of claim 1, wherein the plurality of first doped regions and the second doped region are located at the surface of the semiconductor layer, and wherein a ratio of a surface area occupied by the plurality of first doped regions and the second doped region to a total surface area of the active region of the diode is about 0.3.

11. The semiconductor device of claim 1, wherein a turn-on voltage of a p-n junction between the second doped region and the semiconductor layer is higher than a turn-on voltage of the Schottky junction between the metal layer and the exposed portions of the semiconductor layer.

12. The semiconductor device of claim 1, wherein the first doped regions have a thickness and dopant concentration such that punch-through of p-n junctions between the first doped regions and the semiconductor layer occurs at a lower voltage than breakdown of the Schottky junction between the metal layer and the exposed portions of the semiconductor layer.

13. The semiconductor device of claim 1, further comprising an edge termination region, wherein the first doped regions have a thickness and dopant concentration such that punch-through of p-n junctions between the first doped regions and the semiconductor layer occurs at a lower voltage than a breakdown voltage of the edge termination region.

14. A semiconductor device comprising:

a semiconductor layer having a first conductivity type;

a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer;

a semiconductor region in the semiconductor layer and having a second conductivity type, opposite the first conductivity type, and comprising a plurality of first doped regions arranged as islands in the semiconductor layer;

wherein the first doped regions and the semiconductor layer form respective p-n junctions in parallel with the Schottky junction;

wherein the p-n junctions are configured to generate a depletion region in the semiconductor layer adjacent the Schottky junction when the Schottky junction is reversed biased to limit reverse leakage current through the Schottky junction; and

wherein the p-n junctions are further configured such that punch-through of the p-n junctions occurs at a lower voltage than a breakdown voltage of the Schottky junction.

15. A method of forming a semiconductor device, comprising:

forming a plurality of first doped regions in a semiconductor layer, wherein the semiconductor layer has a first conductivity type and the first doped regions have a second conductivity type opposite the first conductivity type such that the semiconductor layer and the first doped regions form respective p-n junctions, wherein the plurality of first doped regions are arranged as islands in the semiconductor layer; and

forming a metal layer on the semiconductor layer, the metal layer forming a Schottky junction with the semiconductor layer and contacting the first doped regions;

wherein the first doped region have a thickness and dopant concentration such that punch-through of the p-n junctions occurs at a lower voltage than a breakdown voltage of the Schottky junction between the metal layer and the semiconductor layer when the Schottky junction is reversed biased.

16. The method of claim 15, wherein the islands comprise circular islands.

17. The method of claim 15, wherein the islands have irregular shapes.

18. The method of claim 15, wherein the islands have rectangular shapes.

19. The method of claim 15, wherein the islands have polygonal shapes.

20. The method of claim 15, further comprising:

forming a second doped region in the semiconductor layer, the second doped region having a conductivity type opposite the conductivity type of the semiconductor layer and having a dopant concentration higher than the dopant concentration of the first doped region, wherein a second p-n junction between the second doped region and the semiconductor layer is configured to turn on at a voltage that is higher than a turn-on voltage of the Schottky junction between the metal layer and the semiconductor layer.