Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices

• US 20090315083A1
• Filed: 06/20/2008
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Pan, James, Rexer, Christopher Lawrence
• Granted Patent: US 7,807,576 B2
• Time in Patent Office: Days
• US Class Current: 257/280
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.

Claims

1. A method of forming a semiconductor structure which includes a trench gate FET, the method comprising:

forming a plurality of trenches in a semiconductor region using a mask which includes;

(i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer; and

forming a thick bottom dielectric (TBD) along a bottom of each trench, the first oxidation barrier layer preventing formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.

2. The method of claim 1 wherein at least a portion of the second insulating layer remains over and protects the first oxidation barrier layer following formation of the plurality of trenches.

3. The method of claim 1 wherein the second insulating layer is thicker than the first insulating layer.

4. The method of claim 1 wherein the semiconductor region comprises silicon, and the TBD is formed by oxidizing the silicon using a local oxidation of silicon (LOCOS) process.

5. The method of claim 1 further comprising:

forming a second oxidation barrier layer extending along opposing sidewalls of each trench but being discontinuous along the bottom of each trench, the second oxidation barrier layer preventing formation of a dielectric layer along the opposing sidewalls of each trench during formation of the TBD.

6. The method of claim 5 further comprising:

prior to forming the second oxidation barrier layer, forming a third insulating layer along the opposing sidewalls and along the bottom of each trench.

7. The method of claim 5 wherein the first and the second insulating layers comprise oxide.

8. The method of claim 7 wherein the first and the second oxidation barrier layers comprise nitride.

9. The method of claim 1 further comprising:

after forming the plurality of trenches, rounding bottom corners of each trench.

10. The method of claim 9 wherein the semiconductor region comprises silicon, and the bottom corners of each trench are rounded using a silicon etch process, wherein the second insulating layer protects the first oxidation barrier layer during the silicon etch process.

11. The method of claim 1 further comprising:

forming a gate electrode in each trench over and in contact with the TBD.

12. The method of claim 11 wherein the trench gate FET is formed in one or more FET regions of the semiconductor structure, and the semiconductor structure further includes one or more Schottky regions, the method further comprising:

in the one or more FET regions;

forming a body region in the semiconductor region; and

forming source regions in the body region adjacent each trench.

13. The method of claim 12 further comprising:

forming an interconnect layer in the one or more FET regions and in the one or more Schottky regions, the interconnect layer contacting mesa surfaces between adjacent trenches in the one or more Schottky regions to form a Schottky contact, the interconnect layer further contacting the source regions in the one or more FET regions.

14. A method of forming a semiconductor structure which includes a trench gate FET, the method comprising:

forming a plurality of trenches in a semiconductor region using a mask which includes;

(i) a first oxide layer over a surface of the semiconductor region, (ii) a first nitride layer over the first oxide layer, and (iii) a second oxide layer over the first nitride layer;

forming a third oxide layer along opposing sidewalls and bottom of each of the plurality of trenches;

forming nitride spacers along the opposing sidewalls of each trench over the third oxide layer; and

oxidizing silicon to form a thick bottom oxide (TBO) along the bottom of each trench, the first nitride layer preventing formation of oxide along the surface of the semiconductor region during the oxidizing of silicon, and the nitride spacers preventing formation of oxide along the opposing sidewalls of each trench during the oxidizing of silicon.

15. The method of claim 14 wherein at least a portion of the second oxide layer remains over and protects the first nitride layer following formation of the plurality of trenches.

16. The method of claim 14 further comprising:

after forming the plurality of trenches, rounding bottom corners of each trench.

17. The method of claim 16 wherein the semiconductor region comprises silicon, and the bottom corners of each trench are rounded using a silicon etch process, wherein the second oxide layer protects the first nitride layer during the silicon etch process.

18. The method of claim 14 further comprising:

removing the nitride spacers and the third oxide layer from along the opposing sidewalls of each trench;

forming a gate oxide layer along the opposing sidewalls of each trench; and

forming a gate electrode in each trench over and in contact with the TBO.

19. The method of claim 18 wherein the trench gate FET is formed in one or more FET regions of the semiconductor structure, and the semiconductor structure further includes one or more Schottky regions, the method further comprising:

in the one or more FET regions;

forming a body region in the semiconductor region; and

forming source regions in the body region adjacent each trench.

20. The method of claim 19 further comprising:

forming an interconnect layer in the one or more FET regions and in the one or more Schottky regions, the interconnect layer contacting mesa surfaces between adjacent trenches in the one or more Schottky regions to form a Schottky contact, the interconnect layer further contacting the source regions in the one or more FET regions.

21-49. -49. (canceled)

51. A semiconductor structure which includes a shielded gate FET, comprising:

a plurality of trenches in a semiconductor region;

a shield electrode in a bottom portion of each trench;

a gate electrode over the shield electrode;

a shield dielectric lining lower sidewalls of each trench; and

a thick bottom dielectric (TBD) lining a bottom of each trench, wherein a thickness of the TBD is different than a thickness of the shield dielectric.

52. The structure of claim 51 wherein the thickness of the TBD is greater than the thickness of the shield dielectric.

53. The structure of claim 51 further comprising:

an inter-electrode dielectric (IED) extending between the shield electrode and the gate electrode; and

a gate dielectric lining upper sidewalls of each trench on each side of the gate electrode.

54. The structure of claim 53 wherein a thickness of the gate dielectric is less than the thickness of the shield dielectric.

55. The structure of claim 51 wherein the shielded gate FET is in one or more FET regions of the semiconductor structure, and the semiconductor structure further includes one or more Schottky regions, the structure further comprising:

in the one or more FET regions;

a body region in the semiconductor region; and

source regions in the body region adjacent each trench.

56. The structure of claim 55 further comprising:

an interconnect layer extending over the one or more FET regions and over the one or more Schottky regions, the interconnect layer contacting mesa surfaces between adjacent trenches in the one or more Schottky regions to form a Schottky contact, the interconnect layer further contacting the source regions in the one or more FET regions.