TRENCH MOSFET WITH SHALLOW TRENCH FOR GATE CHARGE REDUCTION

• US 20090315103A1
• Filed: 06/20/2008
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Application Number:
  US12/143,714
• Publication Number:
  US 20090315103A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOS device includes shallow trench structure for reduction of gate charge. To counteract the increase of Rds may caused by decreasing the depth of trench, the power MOS device further includes an arsenic Ion Implantation area underneath each trench bottom when N+ red phosphorus substrate is applied, and the concentration of said arsenic doped area is higher than that of epitaxial layer. As the shallow trench is performed, the gate contact trench could be easily etched over to penetrate the gate oxide, which will lead to a shortage of tungsten plug filled in gate contact trench to epitaixial layer. To prevent from this problem, a terrace poly gate is designed in a preferred embodiment of present invention. By using this method, the gate contact trench is lifted to avoid the shortage problem.

Claims

1. A vertical semiconductor power MOS device comprising a plurality of semiconductor power cells with each cell comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein said MOS cell further comprising:

a substrate;

a heavily doped area with the same doping type as epitaxial layer underneath said trench bottom to further reduce Rds;

a source-body contact trench opened through an insulating layer covering said cell structure and extending into said source region and said body region;

a gate contact trench opened through said insulating layer and extending into trench-filling material in said trenched gate underneath gate runner metal;

a plurality of floating trench rings as termination;

a source metal layer formed on a top surface of the MOSFET;

a gate metal layer formed on a top surface of the MOSFET; and

a drain metal layer formed on a bottom surface of the MOSFET.

2. The MOSFET of claim 1, wherein the concentration of said heavily doped region is higher than the concentration of epitaxial layer.

3. The MOSFET of claim 1 wherein said trench gate for gate metal contact is wider than those in active area.

4. The MOSFET of claim 1 wherein said trench-filling material is doped poly.

5. The MOSFET of claim 1 wherein said trench-filling material is combination of doped poly and non-doped poly.

6. The MOSFET of claim 1 wherein said trench-filling material is doped poly with silicide on the poly top.

7. The MOSFET of claim 4 wherein the top level of said doped poly in said gate contact trench is same as that in said trench gates in active area.

8. The MOSFET of claim 4 wherein the top level of said doped poly in said gate contact trench is higher than that in said trench gates in active area, formed by adding additional gate mask.

9. The MOSFET of claim 6 wherein said gate mask is not greater than said gate contact trench for gate metal runner connection.