Trench MOSFET with shallow trench structures

• US 20090315104A1
• Filed: 04/23/2009
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hsieh, Fu-Yuan
• Application Number:
  US12/385,898
• Publication Number:
  US 20090315104A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET with shallow trench structure is disclosed. The improved structure resolves the problem of degradation of BV caused by the As Ion Implantation in termination surface and no additional mask is needed which further enhance the avalanche capability and reduce the manufacture cost.

Claims

1. A vertical semiconductor power MOS device comprising a plurality of semiconductor power cells with each cell comprising a trenched gate surrounded by a source region with first type conductivity encompassed in a body region with second type conductivity above a drain region disposed on a bottom surface of a low-resistivity substrate with first type conductivity, wherein said MOS cell further comprising:

an epitaxial layer with the first type conductivity is grown on the substrate;

an on-resistance reduction doped region underneath said trenched gate bottom with the first type conductivity having doping concentration higher than said epitaxial layer;

a first insulating layer serving as gate oxide lining the inner surface of openings for trench gates;

a second insulating layer functioning as thick oxide interlayer covering top surface of the epitaxial layer;

a source-body contact trench opened through said thick oxide interlayer and said source region, and extending into said body region;

a gate contact trench opened through said thick oxide interlayer and extending into trench-filling material in said trenched gate underneath metal gate runner, which is near termination served as metal field plate over said body region and said epitaxial region;

a tungsten plug filled into said source-body contact trench and said gate contact trench, and padded with a barrier layer.

a source metal layer and a gate metal layer formed over a resistance-reduction layer connected to said tungsten plug in said source-body contact trench and said gate contact trench, respectively;

a drain metal layer formed on a bottom surface of the MOSFET.

2. The MOSFET of claim 1, wherein said metal field plate overlying said body region and said on-resistance reduction region on top of said epitaxial layer.

3. The MOSFET of claim 1, wherein said metal field plate overlying said body region and said epitaxial layer without having said on-resistance reduction region.

4. The MOSFET of claim 1, wherein said trench gate for gate metal contact is wider than those in active area.

5. The MOSFET of claim 1, wherein said trench-filling material is doped poly.

6. The MOSFET of claim 1, wherein said trench-filling material is combination of doped poly and non-doped poly.

7. The MOSFET of claim 1, wherein said trench-filling material is doped poly with silicide on the poly top.

8. The MOSFET of claim 1, wherein the top level of said doped poly in said gate contact trench is same as that in said trench gates in active area.

9. The MOSFET of claim 1, wherein the top level of said doped poly in said gate contact trench is higher than that in said trench gates in active area.

10. The MOSFET of claim 1, wherein said barrier layer in source-body contact trench and gate contact trench is Ti/TiN or Co/TiN.

11. The MOSFET of claim 1, wherein said resistance-reduction layer is Ti or Ti/TiN.

12. A method for manufacturing a vertical semiconductor power device with shallow trench structures comprising the steps of:

growing an epitaxial layer upon a heavily doped substrate, wherein said epitaxial layer and said substrate are doped with a first type dopant, e.g., N dopant;

forming a thick oxide covering front surface of said epitaxial layer as hard mask for later trench bottom Ion Implantation;

forming a trench mask with open and closed areas on the surface of said hard mask;

removing semiconductor material from exposed areas of said trench mask to form a plurality of gate trenches;

growing a sacrificial oxide layer onto the surface of said trenches to remove the plasma damage introduced during opening said trenches;

removing said sacrificial oxide and growing a layer of screen oxide

implanting with As ion to form on-resistance reduction region with a net doping concentration higher than said epitaxial layer;

removing screen oxide layer and said hard mask;

growing a first insulating layer along the front surface of device and the inner surface of said trenches as gate oxide;

depositing doped poly or combination of doped poly and non-doped poly into all trenches onto said gate oxide;

etching back or CMP said gate oxide and said doped poly or combination of doped poly and non-doped poly;

forming body regions by P type ion implantation into the epitaxial layer followed by diffusion to drive in;

forming source regions by N type ion implantation near the top surface of body regions followed by diffusion;

depositing a second insulating layer onto whole surface as thick oxide interlayer;

forming a contact mask on the surface of said second insulating layer and removing the insulating material and semiconductor material;

implanting BF2 ion to form p+ area at the bottom of source-body contact trench within P body region;

depositing Ti/TiN/W or Co/TiN/W consequently into source-body contact trenches and gat contact trench to form source-body contact and trench gate contact;

etching back tungsten and Ti/TiN or Co/TiN;

depositing Al Alloys on front and rear surface of device, respectively, and forming source-metal and gate metal by pattering front metal with a metal mask.

13. The method of claim 12, wherein forming said gate trenches comprises etching said epitaxial layer according to the open areas of said trench mask by dry silicon etching.

14. The method of claim 12, wherein forming said trench gates comprises forming a trench gate with top surface of filling-in material higher than epitaxial layer by offering another gate mask.

15. The method of claim 12, wherein forming a layer of silicide on top of poly as alternative for further reducing gate resistance.

16. A method for manufacturing a vertical semiconductor power device with shallow trench structures comprising the steps of:

growing an epitaxial layer upon a heavily doped substrate, wherein said epitaxial layer and said substrate are doped with a first type dopant, e.g., N dopant;

forming a thick oxide covering front surface of said epitaxial layer as hard mask;

forming a trench mask with open and closed areas on the surface of said hard mask;

removing semiconductor material from exposed areas of said trench mask to form a plurality of gate trenches;

removing said hard mask by wet etch;

growing a sacrificial oxide layer onto the surface of said trenches to remove the plasma damage introduced during opening said trenches;

removing said sacrificial oxide and growing a layer of screen oxide

implanting with As ion to form on-resistance reduction region with a net doping concentration higher than said epitaxial layer;

removing screen oxide layer;

growing a first insulating layer along the front surface of device and the inner surface of said trenches as gate oxide;

depositing doped poly or combination of doped poly and non-doped poly into all trenches onto said gate oxide;

etching back or CMP said gate oxide and said doped poly or combination of doped poly and non-doped poly;

forming body regions by P type ion implantation into the epitaxial layer followed by diffusion to drive in;

forming source regions by N type ion implantation near the top surface of body regions followed by diffusion;

depositing a second insulating layer onto whole surface as thick oxide interlayer;

forming a contact mask on the surface of said second insulating layer and removing the insulating material and semiconductor material;

implanting BF2 ion to form p+ area at the bottom of source-body contact trench within P body region;

depositing Ti/TiN/W or Co/TiN/W consequently into source-body contact trenches and gat contact trench to form source-body contact and trench gate contact;

etching back tungsten and Ti/TiN or Co/TiN;

depositing Al Alloys on front and rear surface of device, respectively, and forming source-metal and gate metal by pattering front metal with a metal mask.

17. The method of claim 16, wherein forming said gate trenches comprises etching said epitaxial layer according to the open areas of said trench mask by dry silicon etching.

18. The method of claim 16, wherein forming said trench gates comprises forming a trench gate with top surface of filling-in material higher than epitaxial layer by offering another gate mask.

19. The method of claim 16, wherein forming a layer of silicide on top of poly as alternative for further reducing gate resistance.