SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT

• US 20090315154A1
• Filed: 06/19/2008
• Published: 12/24/2009
• Est. Priority Date: 06/19/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kirby, Kyle, Parekh, Kunal
• Granted Patent: US 7,968,460 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

Claims

1. A semiconductor device having a top side and a back side comprising:

a first metal layer located between the top side and the back side;

a second metal layer located between the first metal layer and the top side; and

a metal interconnect extending vertically through a portion of the semiconductor device to the back side of semiconductor device, wherein a top region of the metal interconnect is located vertically below a horizontal plane containing the second metal layer.

2. The semiconductor device of claim 1 wherein the first metal layer forms an electrically conductive contact with the metal interconnect.

3. The semiconductor device of claim 1 wherein the second metal layer forms an electrically conductive contact with the metal interconnect.

4. The semiconductor device of claim 1 further comprising a conductive redistribution formed on the back side of the semiconductor device, wherein the conductive redistribution layer is electrically coupled to the metal interconnect.

5. A semiconductor device comprising:

a silicon substrate having top and bottom sides;

active circuitry fabricated on the top side of the silicon substrate and including multiple metal routing layers;

a metal interconnect extending vertically through the silicon substrate to the bottom side such that at least one of the multiple conductive routing layers is located in a horizontal plane located above a top region of the metal interconnect; and

an external electrical interconnect coupled to the metal interconnect at the bottom side of the silicon substrate.

6. The semiconductor device of claim 5 wherein the external electrical interconnect comprising a conductive redistribution formed on the bottom side of the silicon substrate, wherein the conductive redistribution layer is electrically coupled to the metal interconnect.

7. The semiconductor device of claim 5 wherein the conductive redistribution layer comprising a conductive ball bond pad.

8. The semiconductor device of claim 5 wherein the metal interconnect has a length to width ratio of about 5:

1 to 10;

1.

9. The semiconductor device of claim 5 wherein one of the multiple metal routing layers has an electrical connection with the metal interconnect.

10. A method of fabricating a semiconductor device comprising:

etching a via into a semiconductor substrate;

filling the via with a metal material;

forming a metal routing layer subsequent to filling the via; and

removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

11. The method of claim 10 wherein filling the via with a metal material comprises:

forming a metal seed layer;

selectively covering a portion of the metal seed layer such that the metal seed layer located within the via remains exposed; and

plating the exposed metal seed layer.

12. The method of claim 10 further comprises forming a metal redistribution layer on the bottom of the semiconductor substrate such that an electrical connection is formed between the metal filled via and the redistribution layer.

13. The method of claim 10 further comprising forming a second metal routing layer subsequent to forming the metal routing layer, wherein the second metal routing layer forms an electrical contact with the metal filled via.

14. A method of fabricating a semiconductor device comprising:

etching a via into a semiconductor substrate;

insulating the via with a dielectric layer;

filling the insulated via with copper;

forming a first and second metal routing layers subsequent to filling the via, wherein at least one of the metal routing layers forms a physical contact with the copper filled via;

removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the copper filled via; and

forming a metal redistribution layer on the bottom of the semiconductor substrate such that an physical contact is formed between the exposed copper filled via and the redistribution layer.

15. The method of claim 15 wherein filling the via with copper comprises:

forming a copper seed layer;

selectively covering a portion of the copper seed layer such that the copper seed layer located within the insulated via remains exposed; and

plating the exposed copper seed layer.

16. A method of fabricating a semiconductor device comprising:

fabricating a transistor having a gate and source/drain implant regions extending into a top region of a silicon substrate;

forming a dielectric layer above the transistor;

forming a contact extending vertically through the dielectric layer to the transistor;

etching a via through the dielectric layer and into the silicon substrate laterally adjacent to the transistor, wherein the via vertically extends below the source/drain implant regions;

forming a first dielectric layer in the etched via;

forming a metal seed layer after the first dielectric layer;

forming a blocking layer over selected regions of the seed layer located outside of the via;

plating exposed regions of the seed layer to fill the via with metal and form a metal plug;

removing the blocking layer and unplated seed layer;

forming a second dielectric layer over the metal plug;

forming a metal routing layer over the second dielectric area, such that the metal routing layer contacts the metal plug through the second dielectric layer to form an electrical connection;

removing a portion of a bottom side of the silicon substrate to expose a bottom of the metal plug; and

forming a metal redistribution layer on the bottom of the silicon substrate such that an electrical connection is formed between the metal plug and the redistribution layer.

17. The method of claim 16 wherein the metal plug comprises copper.