PREEMPHASIS DRIVER WITH REPLICA BIAS

• US 20090315592A1
• Filed: 06/22/2009
• Published: 12/24/2009
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hidaka, Yasuo
• Granted Patent: US 7,902,883 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0288 the shape being matched to the transmission line pre-equalisation per se H04L25/03343

Abstract

In one embodiment, a system includes a replica driver that includes n-type digital-to-analog converter (NDAC) current sources. The replica driver can produce a reference voltage based on current supplied by the NDAC current sources. The system includes driver fingers that are coupled to the replica driver and each include a driver bias circuit and an output driver. The driver bias circuit includes an operational amplifier (op-amp) that can adjust current-source gate voltage in the output driver to produce voltages at output nodes of the driver fingers that approximately match the reference voltage produced by the replica driver.

Claims

1. A system comprising:

a replica driver that comprises a plurality of n-type digital-to-analog converter (NDAC) current sources, the replica driver being operable to produce a reference voltage based on current supplied by the NDAC current sources; and

a plurality of driver fingers that are coupled to the replica driver and each comprise a driver bias circuit and an output driver, the driver bias circuit comprising an operational amplifier (op-amp) that is operable to adjust current-source gate voltage in the output driver to produce voltages at output nodes of the driver fingers that approximately match the reference voltage produced by the replica driver.

2. The system of claim 1, wherein the replica driver further comprises a plurality of switches that are operable to selectively couple one of the NDAC current sources to a low-output voltage (VOL) node or a high-output voltage (VOH) node of the replica driver.

3. The system of claim 2, wherein:

the replica driver is a low-frequency-period replica driver and the reference voltage is a low-frequency-period reference voltage;

the system further comprises a peak-output-voltage replica driver that comprises another plurality of NDAC current sources, the peak-output-voltage replica driver being operable to produce a peak-output-voltage reference voltage based on current supplied by the other NDAC current sources; and

each one of the driver bias circuits comprises a switch that is operable to selectively couple an input of the op-amp in the driver bias circuit to the low-frequency-period reference voltage or the peak-output-voltage reference voltage.

4. The system of claim 1, wherein the output driver is a common gate (CG) driver.

5. The system of claim 1, wherein the output driver is a current mode logic (CML) driver.

6. The system of claim 1, wherein the NDAC current source is an n-type metal-oxide-semiconductor (NMOS) digital-to-analog converter (NDAC) current source.

7. The system of claim 1, wherein the driver fingers are preemphasis driver fingers.

8. The system of claim 1, wherein there are three NDAC current sources in the replica driver.

9. The system of claim 1, wherein there are three driver fingers.

10. The system of claim 1, wherein the reference voltage is a low-output voltage (VOL).

11. The system of claim 1, wherein:

each of the driver bias circuits comprises a p-type digital-to-analog converter (PDAC) current source; and

each of the NDAC current sources corresponds to a particular one of the driver bias circuits, a first current of the NDAC current source mirroring a second current of the PDAC in the particular one of the driver bias circuits corresponding to the NDAC current source.

12. The system of claim 1, wherein a replica bias circuit in the replica driver comprises a plurality of replica resistors, each replica resistor having a first resistance value that is a multiple of a second resistance value of a driver output resistor coupled to the output nodes of the driver fingers.

13. A method comprising:

by a replica driver that comprises a plurality of n-type digital-to-analog converter (NDAC) current sources, producing a reference voltage based on current supplied by the NDAC current sources; and

by an operational amplifier (op-amp) in a driver bias circuit in each of a plurality of driver fingers that are coupled to the replica driver, adjusting current-source gate voltage in the output driver to produce voltages at output nodes of the driver fingers that approximately match the reference voltage produced by the replica driver.

14. The method of claim 13, further comprising, by a plurality of switches in the replica driver, selectively coupling one of the NDAC current sources to a low-output voltage (VOL) node or a high-output voltage (VOH) node of the replica driver.

15. The method of claim 14, wherein:

the replica driver is a low-frequency-period replica driver and the reference voltage is a low-frequency-period reference voltage; and

the method further comprises;

by a peak-output-voltage replica driver that comprises another plurality of NDAC current sources, producing a peak-output-voltage reference voltage based on current supplied by the other NDAC current sources; and

by a switch in each one of the driver bias circuits, selectively coupling an input of the op-amp in the driver bias circuit to the low-frequency-period reference voltage or the peak-output-voltage reference voltage.

16. The method of claim 13, wherein the output driver is a common gate (CG) driver.

17. The method of claim 13, wherein the output driver is a current mode logic (CML) driver.

18. The method of claim 13, wherein the NDAC current source is an n-type metal-oxide-semiconductor (NMOS) digital-to-analog converter (NDAC) current source.

19. The method of claim 13, wherein the driver fingers are preemphasis driver fingers.

20. The method of claim 13, wherein there are three NDAC current sources in the replica driver.

21. The method of claim 13 wherein there are three driver fingers.

22. The method of claim 13, wherein the reference voltage is a low-output voltage (VOL).

23. The method of claim 13, wherein:

each of the driver bias circuits comprises a p-type digital-to-analog converter (PDAC) current source; and

each of the NDAC current sources corresponds to a particular one of the driver bias circuits, a first current of the NDAC current source mirroring a second current of the PDAC in the particular one of the driver bias circuits corresponding to the NDAC current source.

24. The method of claim 13, wherein a replica bias circuit in the replica driver comprises a plurality of replica resistors, each replica resistor having a first resistance value that is a multiple of a second resistance value of a driver output resistor coupled to the output nodes of the driver fingers.

25. A system comprising:

a replica driver that comprises a plurality of n-type digital-to-analog converter (NDAC) current sources, the replica driver being operable to produce a low-output reference voltage (VOL) based on current supplied by the NDAC current sources; and

a plurality of preemphasis driver fingers that are coupled to the replica driver and each comprise a driver bias circuit and a common gate (CG) driver, the driver bias circuit comprising an operational amplifier (op-amp) and a p-type digital-to-analog converter (PDAC) current source, the op-amp being operable to adjust current-source gate voltage in the CG driver to produce voltages at output nodes of the preemphasis driver fingers that approximately match VOL;

wherein;

each of the NDAC current sources corresponds to a particular one of the driver bias circuits, a first current of the NDAC current source mirroring a second current of the PDAC in the particular one of the driver bias circuits corresponding to the NDAC current source; and

a replica bias circuit in the replica driver comprises a plurality of replica resistors, each replica resistor having a first resistance value that is a multiple of a second resistance value of a driver output resistor coupled to the output nodes of the driver fingers.